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Commit d9e2b8ec authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: npucc-kona: Add support for V2 frequencies"

parents 4e1dd5e8 3a59e324

drivers/clk/qcom/camcc-kona.c

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ 
	.ib = _ib,				\

}



static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM_MM, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);



static struct msm_bus_vectors clk_debugfs_vectors[] = {

drivers/clk/qcom/dispcc-kona.c

+1 −1
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ 


#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }



static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM_MM, 1, vdd_corner);



#define MSM_BUS_VECTOR(_src, _dst, _ab, _ib)	\

{						\

drivers/clk/qcom/gcc-kona.c

+1 −1
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ 


static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_cx_ao, VDD_NUM, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM_MM, 1, vdd_corner);



enum {

	P_BI_TCXO,

drivers/clk/qcom/npucc-kona.c

+56 −16
Original line number Diff line number Diff line
@@ -120,12 +120,12 @@ static const u32 crc_reg_val[] = { 
};



static struct alpha_pll_config npu_cc_pll0_config = {

	.l = 0x14,

	.l = 0x1F,

	.cal_l = 0x44,

	.alpha = 0xD555,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -184,7 +184,7 @@ static struct alpha_pll_config npu_cc_pll1_config = { 
	.alpha = 0x2000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -235,12 +235,12 @@ static struct clk_alpha_pll_postdiv npu_cc_pll1_out_even = { 
};



static struct alpha_pll_config npu_q6ss_pll_config = {

	.l = 0xD,

	.l = 0xF,

	.cal_l = 0x44,

	.alpha = 0x555,

	.alpha = 0xA000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -282,7 +282,6 @@ static struct clk_fixed_factor npu_cc_crc_div = { 
};



static const struct freq_tbl ftbl_npu_cc_cal_hm0_clk_src[] = {

	F(200000000, P_NPU_CC_CRC_DIV, 1, 0, 0),

	F(300000000, P_NPU_CC_CRC_DIV, 1, 0, 0),

	F(466000000, P_NPU_CC_CRC_DIV, 1, 0, 0),

	F(533000000, P_NPU_CC_CRC_DIV, 1, 0, 0),
@@ -291,6 +290,16 @@ static const struct freq_tbl ftbl_npu_cc_cal_hm0_clk_src[] = { 
	{ }

};



static const struct freq_tbl ftbl_npu_cc_cal_hm0_clk_src_kona_v2[] = {

	F(300000000, P_NPU_CC_CRC_DIV, 1, 0, 0),

	F(406000000, P_NPU_CC_CRC_DIV, 1, 0, 0),

	F(533000000, P_NPU_CC_CRC_DIV, 1, 0, 0),

	F(730000000, P_NPU_CC_CRC_DIV, 1, 0, 0),

	F(920000000, P_NPU_CC_CRC_DIV, 1, 0, 0),

	F(1000000000, P_NPU_CC_CRC_DIV, 1, 0, 0),

	{ }

};



static struct clk_rcg2 npu_cc_cal_hm1_clk_src = {

	.cmd_rcgr = 0x1140,

	.mnd_width = 0,
@@ -308,7 +317,6 @@ static struct clk_rcg2 npu_cc_cal_hm1_clk_src = { 
		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 200000000,

			[VDD_LOWER] = 300000000,

			[VDD_LOW] = 466000000,

			[VDD_LOW_L1] = 533000000,
@@ -335,7 +343,6 @@ static struct clk_rcg2 npu_cc_cal_hm0_clk_src = { 
			.vdd_class = &vdd_cx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 200000000,

				[VDD_LOWER] = 300000000,

				[VDD_LOW] = 466000000,

				[VDD_LOW_L1] = 533000000,
@@ -352,7 +359,6 @@ static struct clk_rcg2 npu_cc_cal_hm0_clk_src = { 
};



static const struct freq_tbl ftbl_npu_cc_core_clk_src[] = {

	F(60000000, P_GCC_NPU_GPLL0_DIV_CLK, 5, 0, 0),

	F(100000000, P_GCC_NPU_GPLL0_DIV_CLK, 3, 0, 0),

	F(200000000, P_GCC_NPU_GPLL0_CLK, 3, 0, 0),

	F(333333333, P_NPU_CC_PLL1_OUT_EVEN, 4.5, 0, 0),
@@ -378,7 +384,6 @@ static struct clk_rcg2 npu_cc_core_clk_src = { 
		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 60000000,

			[VDD_LOWER] = 100000000,

			[VDD_LOW] = 200000000,

			[VDD_LOW_L1] = 333333333,
@@ -388,7 +393,6 @@ static struct clk_rcg2 npu_cc_core_clk_src = { 
};



static const struct freq_tbl ftbl_npu_cc_lmh_clk_src[] = {

	F(60000000, P_GCC_NPU_GPLL0_DIV_CLK, 5, 0, 0),

	F(100000000, P_GCC_NPU_GPLL0_DIV_CLK, 3, 0, 0),

	F(200000000, P_GCC_NPU_GPLL0_CLK, 3, 0, 0),

	F(214285714, P_NPU_CC_PLL1_OUT_EVEN, 7, 0, 0),
@@ -413,7 +417,6 @@ static struct clk_rcg2 npu_cc_lmh_clk_src = { 
		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 60000000,

			[VDD_LOWER] = 100000000,

			[VDD_LOW] = 200000000,

			[VDD_LOW_L1] = 214285714,
@@ -441,7 +444,6 @@ static struct clk_rcg2 npu_cc_xo_clk_src = { 
};



static const struct freq_tbl ftbl_npu_dsp_core_clk_src[] = {

	F(250000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(300000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(400000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(500000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),
@@ -467,7 +469,6 @@ static struct clk_rcg2 npu_dsp_core_clk_src = { 
		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 250000000,

			[VDD_LOWER] = 300000000,

			[VDD_LOW] = 400000000,

			[VDD_LOW_L1] = 500000000,
@@ -1168,10 +1169,45 @@ static const struct qcom_cc_desc npu_qdsp6ss_pll_kona_desc = { 


static const struct of_device_id npu_cc_kona_match_table[] = {

	{ .compatible = "qcom,npucc-kona" },

	{ .compatible = "qcom,npucc-kona-v2" },

	{ }

};

MODULE_DEVICE_TABLE(of, npu_cc_kona_match_table);



static void npu_cc_kona_fixup_konav2(struct regmap *regmap)

{

	npu_cc_cal_hm0_clk_src.freq_tbl = ftbl_npu_cc_cal_hm0_clk_src_kona_v2;

	npu_cc_cal_hm0_clk_src.clkr.hw.init->rate_max[VDD_LOW] = 406000000;

	npu_cc_cal_hm0_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] = 730000000;

	npu_cc_cal_hm0_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL_L1] =

		850000000;

	npu_cc_cal_hm0_clk_src.clkr.hw.init->rate_max[VDD_HIGH] = 920000000;

	npu_cc_cal_hm0_clk_src.clkr.hw.init->rate_max[VDD_HIGH_L1] = 1000000000;

	npu_cc_cal_hm1_clk_src.freq_tbl = ftbl_npu_cc_cal_hm0_clk_src_kona_v2;

	npu_cc_cal_hm1_clk_src.clkr.hw.init->rate_max[VDD_LOW] = 406000000;

	npu_cc_cal_hm1_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] = 730000000;

	npu_cc_cal_hm1_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL_L1] =

		850000000;

	npu_cc_cal_hm1_clk_src.clkr.hw.init->rate_max[VDD_HIGH] = 920000000;

	npu_cc_cal_hm1_clk_src.clkr.hw.init->rate_max[VDD_HIGH_L1] = 1000000000;

}



static int npu_cc_kona_fixup(struct platform_device *pdev,

	struct regmap *regmap)

{

	const char *compat = NULL;

	int compatlen = 0;



	compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);

	if (!compat || (compatlen <= 0))

		return -EINVAL;



	if (!strcmp(compat, "qcom,npucc-kona-v2"))

		npu_cc_kona_fixup_konav2(regmap);



	return 0;

}



static int npu_clocks_kona_probe(struct platform_device *pdev,

				 const struct qcom_cc_desc *desc)

{
@@ -1203,6 +1239,10 @@ static int npu_clocks_kona_probe(struct platform_device *pdev, 
				ret);

			return ret;

		}



		ret = npu_cc_kona_fixup(pdev, regmap);

		if (ret)

			return ret;

	} else if (!strcmp("qdsp6ss_pll", desc->config->name)) {

		clk_lucid_pll_configure(&npu_q6ss_pll, regmap,

					&npu_q6ss_pll_config);

drivers/clk/qcom/vdd-level.h

+6 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 */



#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_H
@@ -16,7 +16,10 @@ enum vdd_levels { 
	VDD_LOW,		/* SVS */

	VDD_LOW_L1,		/* SVSL1 */

	VDD_NOMINAL,		/* NOM */

	VDD_NOMINAL_L1,		/* NOM L1 */

	VDD_HIGH,		/* TURBO */

	VDD_HIGH_L1,		/* TURBO L1 */

	VDD_NUM_MM = VDD_HIGH_L1,

	VDD_NUM,

};
@@ -27,7 +30,9 @@ static int vdd_corner[] = { 
	[VDD_LOW]     = RPMH_REGULATOR_LEVEL_SVS,

	[VDD_LOW_L1]  = RPMH_REGULATOR_LEVEL_SVS_L1,

	[VDD_NOMINAL] = RPMH_REGULATOR_LEVEL_NOM,

	[VDD_NOMINAL_L1] = RPMH_REGULATOR_LEVEL_NOM_L1,

	[VDD_HIGH]    = RPMH_REGULATOR_LEVEL_TURBO,

	[VDD_HIGH_L1]    = RPMH_REGULATOR_LEVEL_TURBO_L1,

};



#endif