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Commit d9b59e78 authored by Sharat Masetty's avatar Sharat Masetty
Browse files

ARM: dts: msm: Add speed bin support for A620 

This patch adds support to parse various speed bins for A620
based on the fuse definitions.

Change-Id: I32360ab77b8e654fe72a546827d89cb34c64f061
parent 2551ba81

qcom/lito-gpu.dtsi

+154 −38
Original line number Diff line number Diff line
@@ -192,13 +192,81 @@ 
			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

		/*

		 * Speed-bin zero is default speed bin.

		 * For rest of the speed bins, speed-bin value

		 * is calulated as FMAX/4.8 MHz round up to zero

		 * decimal places.

		 */

		qcom,gpu-pwrlevel-bins {

			#address-cells = <1>;

			#size-cells = <0>;



			compatible = "qcom,gpu-pwrlevels";

			compatible="qcom,gpu-pwrlevel-bins";



			qcom,gpu-pwrlevels-0 {

				#address-cells = <1>;

				#size-cells = <0>;



				qcom,speed-bin = <0>;

				qcom,ca-target-pwrlevel = <2>;

				qcom,initial-pwrlevel = <3>;



				/* NOM */

				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <625000000>;

					qcom,bus-freq = <11>;

					qcom,bus-min = <10>;

					qcom,bus-max = <12>;

				};



				/* SVS L1 */

				qcom,gpu-pwrlevel@1 {

					reg = <1>;

					qcom,gpu-freq = <500000000>;

					qcom,bus-freq = <9>;

					qcom,bus-min = <8>;

					qcom,bus-max = <11>;

				};



				/* SVS */

				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <400000000>;

					qcom,bus-freq = <8>;

					qcom,bus-min = <6>;

					qcom,bus-max = <9>;

				};



				/* Low SVS */

				qcom,gpu-pwrlevel@3 {

					reg = <3>;

					qcom,gpu-freq = <275000000>;

					qcom,bus-freq = <6>;

					qcom,bus-min = <6>;

					qcom,bus-max = <8>;

				};



				qcom,gpu-pwrlevel@4 {

					reg = <4>;

					qcom,gpu-freq = <0>;

					qcom,bus-freq = <0>;

					qcom,bus-min = <0>;

					qcom,bus-max = <0>;

				};

			};



			qcom,gpu-pwrlevels-1 {

				#address-cells = <1>;

				#size-cells = <0>;



				qcom,speed-bin = <132>;



				qcom,initial-pwrlevel = <3>;

				qcom,ca-target-pwrlevel = <2>;



				/* NOM */

				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <625000000>;
@@ -207,6 +275,7 @@ 
					qcom,bus-max = <12>;

				};



				/* SVS L1 */

				qcom,gpu-pwrlevel@1 {

					reg = <1>;

					qcom,gpu-freq = <500000000>;
@@ -215,6 +284,7 @@ 
					qcom,bus-max = <11>;

				};



				/* SVS */

				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <400000000>;
@@ -223,6 +293,7 @@ 
					qcom,bus-max = <9>;

				};



				/* Low SVS */

				qcom,gpu-pwrlevel@3 {

					reg = <3>;

					qcom,gpu-freq = <275000000>;
@@ -239,6 +310,51 @@ 
					qcom,bus-max = <0>;

				};

			};



			qcom,gpu-pwrlevels-3 {

				#address-cells = <1>;

				#size-cells = <0>;



				qcom,speed-bin = <115>;

				qcom,initial-pwrlevel = <2>;

				qcom,ca-target-pwrlevel = <1>;



				/* SVS L1 */

				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <500000000>;

					qcom,bus-freq = <9>;

					qcom,bus-min = <8>;

					qcom,bus-max = <12>;

				};



				/* SVS */

				qcom,gpu-pwrlevel@1 {

					reg = <1>;

					qcom,gpu-freq = <400000000>;

					qcom,bus-freq = <8>;

					qcom,bus-min = <6>;

					qcom,bus-max = <9>;

				};



				/* Low SVS */

				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <275000000>;

					qcom,bus-freq = <6>;

					qcom,bus-min = <6>;

					qcom,bus-max = <8>;

				};



				qcom,gpu-pwrlevel@3 {

					reg = <3>;

					qcom,gpu-freq = <0>;

					qcom,bus-freq = <0>;

					qcom,bus-min = <0>;

					qcom,bus-max = <0>;

				};

			};

		};

	};



	kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {