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Commit d9a9a23f authored by Linus Torvalds's avatar Linus Torvalds
Browse files
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (23 commits)
  [POWERPC] Remove leftover printk in isa-bridge.c
  [POWERPC] Remove duplicate #include
  [POWERPC] Initialize lockdep earlier
  [POWERPC] Document when printk is useable
  [POWERPC] Fix bogus paca->_current initialization
  [POWERPC] Fix of_i2c include for module compilation
  [POWERPC] Make default cputable entries reflect selected CPU family
  [POWERPC] spufs: lockdep annotations for spufs_dir_close
  [POWERPC] spufs: don't requeue victim contex in find_victim if it's not in spu_run
  [POWERPC] 4xx: Fix PCI mem in sequoia DTS
  [POWERPC] 4xx: Add endpoint support to 4xx PCIe driver
  [POWERPC] 4xx: Fix problem with new TLB storage attibute fields on 440x6 core
  [POWERPC] spufs: spu_create should send inotify IM_CREATE event
  [POWERPC] spufs: handle faults while the context switch pending flag is set
  [POWERPC] spufs: fix concurrent delivery of class 0 & 1 exceptions
  [POWERPC] spufs: try to route SPU interrupts to local node
  [POWERPC] spufs: set SPU_CONTEXT_SWITCH_PENDING before synchronising SPU irqs
  [POWERPC] spufs: don't acquire state_mutex interruptible while performing callback
  [POWERPC] spufs: update master runcntl with context lock held
  [POWERPC] spufs: fix post-stopped update of MFC_CNTL register
  ...
parents 9b013c28 53962ecf
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+7 −2
Original line number Diff line number Diff line
@@ -342,9 +342,14 @@
			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed. Chip supports a second
			 * IO range but we don't use it for now
			 * From the 440EPx user manual:
			 * PCI 1 Memory     1 8000 0000     1 BFFF FFFF     1GB
			 * I/O              1 E800 0000     1 E800 FFFF     64KB
			 * I/O              1 E880 0000     1 EBFF FFFF     56MB
			 */
			ranges = <02000000 0 80000000 1 80000000 0 10000000
				01000000 0 00000000 1 e8000000 0 00100000>;
			ranges = <02000000 0 80000000 1 80000000 0 40000000
				01000000 0 00000000 1 e8000000 0 00010000
				01000000 0 00000000 1 e8800000 0 03800000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <42000000 0 0 0 0 0 80000000>;
+0 −1
Original line number Diff line number Diff line
@@ -16,7 +16,6 @@
#include <asm/mmu.h>
#include <asm/pgtable.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/processor.h>
#include <asm/udbg.h>

+43 −10
Original line number Diff line number Diff line
@@ -1208,6 +1208,18 @@ static struct cpu_spec __initdata cpu_specs[] = {
		.machine_check		= machine_check_4xx,
		.platform		= "ppc405",
	},
	{	/* default match */
		.pvr_mask		= 0x00000000,
		.pvr_value		= 0x00000000,
		.cpu_name		= "(generic 40x PPC)",
		.cpu_features		= CPU_FTRS_40X,
		.cpu_user_features	= PPC_FEATURE_32 |
			PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
		.icache_bsize		= 32,
		.dcache_bsize		= 32,
		.machine_check		= machine_check_4xx,
		.platform		= "ppc405",
	}

#endif /* CONFIG_40x */
#ifdef CONFIG_44x
@@ -1421,8 +1433,18 @@ static struct cpu_spec __initdata cpu_specs[] = {
		.machine_check		= machine_check_440A,
		.platform		= "ppc440",
	},
	{	/* default match */
		.pvr_mask		= 0x00000000,
		.pvr_value		= 0x00000000,
		.cpu_name		= "(generic 44x PPC)",
		.cpu_features		= CPU_FTRS_44X,
		.cpu_user_features	= COMMON_USER_BOOKE,
		.icache_bsize		= 32,
		.dcache_bsize		= 32,
		.machine_check		= machine_check_4xx,
		.platform		= "ppc440",
	}
#endif /* CONFIG_44x */
#ifdef CONFIG_FSL_BOOKE
#ifdef CONFIG_E200
	{	/* e200z5 */
		.pvr_mask		= 0xfff00000,
@@ -1451,7 +1473,19 @@ static struct cpu_spec __initdata cpu_specs[] = {
		.machine_check		= machine_check_e200,
		.platform		= "ppc5554",
	},
#elif defined(CONFIG_E500)
	{	/* default match */
		.pvr_mask		= 0x00000000,
		.pvr_value		= 0x00000000,
		.cpu_name		= "(generic E200 PPC)",
		.cpu_features		= CPU_FTRS_E200,
		.cpu_user_features	= COMMON_USER_BOOKE |
			PPC_FEATURE_HAS_EFP_SINGLE |
			PPC_FEATURE_UNIFIED_CACHE,
		.dcache_bsize		= 32,
		.machine_check		= machine_check_e200,
		.platform		= "ppc5554",
#endif /* CONFIG_E200 */
#ifdef CONFIG_E500
	{	/* e500 */
		.pvr_mask		= 0xffff0000,
		.pvr_value		= 0x80200000,
@@ -1487,20 +1521,19 @@ static struct cpu_spec __initdata cpu_specs[] = {
		.machine_check		= machine_check_e500,
		.platform		= "ppc8548",
	},
#endif
#endif
#if !CLASSIC_PPC
	{	/* default match */
		.pvr_mask		= 0x00000000,
		.pvr_value		= 0x00000000,
		.cpu_name		= "(generic PPC)",
		.cpu_features		= CPU_FTRS_GENERIC_32,
		.cpu_user_features	= PPC_FEATURE_32,
		.cpu_name		= "(generic E500 PPC)",
		.cpu_features		= CPU_FTRS_E500,
		.cpu_user_features	= COMMON_USER_BOOKE |
			PPC_FEATURE_HAS_SPE_COMP |
			PPC_FEATURE_HAS_EFP_SINGLE_COMP,
		.icache_bsize		= 32,
		.dcache_bsize		= 32,
		.machine_check		= machine_check_e500,
		.platform		= "powerpc",
	}
#endif /* !CLASSIC_PPC */
#endif /* CONFIG_E500 */
#endif /* CONFIG_PPC32 */
};

+8 −1
Original line number Diff line number Diff line
@@ -653,7 +653,14 @@ finish_tlb_load:
	rlwimi	r10, r11, 0, 26, 26		/* UX = HWEXEC & USER */

	rlwimi	r12, r10, 0, 26, 31		/* Insert static perms */
	rlwinm	r12, r12, 0, 20, 15		/* Clear U0-U3 */

	/*
	 * Clear U0-U3 and WL1 IL1I IL1D IL2I IL2D bits which are added
	 * on newer 440 cores like the 440x6 used on AMCC 460EX/460GT (see
	 * include/asm-powerpc/pgtable-ppc32.h for details).
	 */
	rlwinm	r12, r12, 0, 20, 10

	tlbwe	r12, r13, PPC44x_TLB_ATTRIB	/* Write ATTRIB */

	/* Done...restore registers and get out of here.
+0 −4
Original line number Diff line number Diff line
@@ -1517,10 +1517,6 @@ _INIT_STATIC(start_here_multiplatform)
	addi	r2,r2,0x4000
	add	r2,r2,r26

	/* Set initial ptr to current */
	LOAD_REG_IMMEDIATE(r4, init_task)
	std	r4,PACACURRENT(r13)

	/* Do very early kernel initializations, including initial hash table,
	 * stab and slb setup before we turn on relocation.	*/

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