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Commit d969c155 authored by John Keeping's avatar John Keeping Committed by Sean Paul
Browse files

drm/rockchip: dw-mipi-dsi: configure PHY before enabling 



The bias, bandgap and PLL should all be configured before we enable
them.

Signed-off-by: default avatarJohn Keeping <john@metanate.com>
Reviewed-by: default avatarSean Paul <seanpaul@chromium.org>
Signed-off-by: default avatarSean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-16-john@metanate.com
parent efe83cee

drivers/gpu/drm/rockchip/dw-mipi-dsi.c

+6 −5
Original line number Diff line number Diff line
@@ -413,12 +413,17 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 


	dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));



	dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);

	dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));

	dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |

					 LOW_PROGRAM_EN);

	dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |

					 HIGH_PROGRAM_EN);

	dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);



	dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |

					 BIASEXTR_SEL(BIASEXTR_127_7));

	dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |

					 BANDGAP_SEL(BANDGAP_96_10));



	dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |

					 BIAS_BLOCK_ON | BANDGAP_ON);
@@ -429,10 +434,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 
					 SETRD_MAX | POWER_MANAGE |

					 TER_RESISTORS_ON);



	dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |

					 BIASEXTR_SEL(BIASEXTR_127_7));

	dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |

					 BANDGAP_SEL(BANDGAP_96_10));



	dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);

	dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);