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Commit d961db75 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/ttm: restructure to allow driver to plug in alternate memory manager 



Nouveau will need this on GeForce 8 and up to account for the GPU
reordering physical VRAM for some memory types.

Reviewed-by: default avatarJerome Glisse <jglisse@redhat.com>
Acked-by: default avatarThomas Hellström <thellstrom@vmware.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 42311ff9

drivers/gpu/drm/nouveau/nouveau_bo.c

+10 −8
Original line number Diff line number Diff line
@@ -381,6 +381,7 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 
		man->default_caching = TTM_PL_FLAG_CACHED;

		break;

	case TTM_PL_VRAM:

		man->func = &ttm_bo_manager_func;

		man->flags = TTM_MEMTYPE_FLAG_FIXED |

			     TTM_MEMTYPE_FLAG_MAPPABLE;

		man->available_caching = TTM_PL_FLAG_UNCACHED |
@@ -392,6 +393,7 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 
			man->gpu_offset = 0;

		break;

	case TTM_PL_TT:

		man->func = &ttm_bo_manager_func;

		switch (dev_priv->gart_info.type) {

		case NOUVEAU_GART_AGP:

			man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
@@ -494,8 +496,8 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 
	u64 src_offset, dst_offset;

	int ret;



	src_offset = old_mem->mm_node->start << PAGE_SHIFT;

	dst_offset = new_mem->mm_node->start << PAGE_SHIFT;

	src_offset = old_mem->start << PAGE_SHIFT;

	dst_offset = new_mem->start << PAGE_SHIFT;

	if (!nvbo->no_vm) {

		if (old_mem->mem_type == TTM_PL_VRAM)

			src_offset += dev_priv->vm_vram_base;
@@ -597,8 +599,8 @@ static int 
nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,

		  struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)

{

	u32 src_offset = old_mem->mm_node->start << PAGE_SHIFT;

	u32 dst_offset = new_mem->mm_node->start << PAGE_SHIFT;

	u32 src_offset = old_mem->start << PAGE_SHIFT;

	u32 dst_offset = new_mem->start << PAGE_SHIFT;

	u32 page_count = new_mem->num_pages;

	int ret;
@@ -746,7 +748,7 @@ nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, 
		return 0;

	}



	offset = new_mem->mm_node->start << PAGE_SHIFT;

	offset = new_mem->start << PAGE_SHIFT;



	if (dev_priv->card_type == NV_50) {

		ret = nv50_mem_vm_bind_linear(dev,
@@ -860,14 +862,14 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 
	case TTM_PL_TT:

#if __OS_HAS_AGP

		if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {

			mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;

			mem->bus.offset = mem->start << PAGE_SHIFT;

			mem->bus.base = dev_priv->gart_info.aper_base;

			mem->bus.is_iomem = true;

		}

#endif

		break;

	case TTM_PL_VRAM:

		mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;

		mem->bus.offset = mem->start << PAGE_SHIFT;

		mem->bus.base = pci_resource_start(dev->pdev, 1);

		mem->bus.is_iomem = true;

		break;
@@ -897,7 +899,7 @@ nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) 
	}



	/* make sure bo is in mappable vram */

	if (bo->mem.mm_node->start + bo->mem.num_pages < dev_priv->fb_mappable_pages)

	if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)

		return 0;

drivers/gpu/drm/nouveau/nouveau_channel.c

+3 −3
Original line number Diff line number Diff line
@@ -48,14 +48,14 @@ nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan) 
						  dev_priv->gart_info.aper_size,

						  NV_DMA_ACCESS_RO, &pushbuf,

						  NULL);

		chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT;

		chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;

	} else

	if (dev_priv->card_type != NV_04) {

		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,

					     dev_priv->fb_available_size,

					     NV_DMA_ACCESS_RO,

					     NV_DMA_TARGET_VIDMEM, &pushbuf);

		chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT;

		chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;

	} else {

		/* NV04 cmdbuf hack, from original ddx.. not sure of it's

		 * exact reason for existing :)  PCI access to cmdbuf in
@@ -67,7 +67,7 @@ nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan) 
					     dev_priv->fb_available_size,

					     NV_DMA_ACCESS_RO,

					     NV_DMA_TARGET_PCI, &pushbuf);

		chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT;

		chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;

	}



	nouveau_gpuobj_ref(pushbuf, &chan->pushbuf);

drivers/gpu/drm/nouveau/nouveau_notifier.c

+1 −1
Original line number Diff line number Diff line
@@ -113,7 +113,7 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle, 
		return -ENOMEM;

	}



	offset = chan->notifier_bo->bo.mem.mm_node->start << PAGE_SHIFT;

	offset = chan->notifier_bo->bo.mem.start << PAGE_SHIFT;

	if (chan->notifier_bo->bo.mem.mem_type == TTM_PL_VRAM) {

		target = NV_DMA_TARGET_VIDMEM;

	} else

drivers/gpu/drm/nouveau/nouveau_sgdma.c

+2 −2
Original line number Diff line number Diff line
@@ -95,9 +95,9 @@ nouveau_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem) 
	struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;

	unsigned i, j, pte;



	NV_DEBUG(dev, "pg=0x%lx\n", mem->mm_node->start);

	NV_DEBUG(dev, "pg=0x%lx\n", mem->start);



	pte = nouveau_sgdma_pte(nvbe->dev, mem->mm_node->start << PAGE_SHIFT);

	pte = nouveau_sgdma_pte(nvbe->dev, mem->start << PAGE_SHIFT);

	nvbe->pte_start = pte;

	for (i = 0; i < nvbe->nr_pages; i++) {

		dma_addr_t dma_offset = nvbe->pages[i];

drivers/gpu/drm/nouveau/nv50_crtc.c

+1 −2
Original line number Diff line number Diff line
@@ -104,8 +104,7 @@ nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked) 
		OUT_RING(evo, nv_crtc->lut.depth == 8 ?

				NV50_EVO_CRTC_CLUT_MODE_OFF :

				NV50_EVO_CRTC_CLUT_MODE_ON);

		OUT_RING(evo, (nv_crtc->lut.nvbo->bo.mem.mm_node->start <<

				 PAGE_SHIFT) >> 8);

		OUT_RING(evo, (nv_crtc->lut.nvbo->bo.mem.start << PAGE_SHIFT) >> 8);

		if (dev_priv->chipset != 0x50) {

			BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);

			OUT_RING(evo, NvEvoVRAM);