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Commit d91ca84e authored by Chaotian Jing's avatar Chaotian Jing Committed by Ulf Hansson
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mmc: dt-bindings: Add reg/source_cg/latch-ck for Mediatek MMC bindings 



Change the comptiable for support of multi-platform
Make compatible explicit, as MMC host of mt8173 has difference with
mt8135(mt8173 supports hs400 and hs400_tune),so that need separate
mt8173/mt8135 compatible name.
Add description for reg
Add description for source_cg
Add description for mediatek,latch-ck
Note that source_cg and mediatek,latch-ck are optional for some projects,
eg, MT2701 do not have source_cg, and MT2712 do not need
mediatek,latch-ck

Signed-off-by: default avatarChaotian Jing <chaotian.jing@mediatek.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Tested-by: default avatarSean Wang <sean.wang@mediatek.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 361eeda0

Documentation/devicetree/bindings/mmc/mtk-sd.txt

+15 −3
Original line number Diff line number Diff line
@@ -7,10 +7,18 @@ This file documents differences between the core properties in mmc.txt 
and the properties used by the msdc driver.



Required properties:

- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc"

- compatible: value should be either of the following.

	"mediatek,mt8135-mmc": for mmc host ip compatible with mt8135

	"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173

	"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701

	"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712

- reg: physical base address of the controller and length

- interrupts: Should contain MSDC interrupt number

- clocks: MSDC source clock, HCLK

- clock-names: "source", "hclk"

- clocks: Should contain phandle for the clock feeding the MMC controller

- clock-names: Should contain the following:

	"source" - source clock (required)

	"hclk" - HCLK which used for host (required)

	"source_cg" - independent source clock gate (required for MT2712)

- pinctrl-names: should be "default", "state_uhs"

- pinctrl-0: should contain default/high speed pin ctrl

- pinctrl-1: should contain uhs mode pin ctrl
@@ -30,6 +38,10 @@ Optional properties: 
- mediatek,hs400-cmd-resp-sel-rising:  HS400 command response sample selection

				       If present,HS400 command responses are sampled on rising edges.

				       If not present,HS400 command responses are sampled on falling edges.

- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc

		     error caused by stop clock(fifo full)

		     Valid range = [0:0x7]. if not present, default value is 0.

		     applied to compatible "mediatek,mt2701-mmc".



Examples:

mmc0: mmc@11230000 {