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Commit d8f57aa4 authored by Will Deacon's avatar Will Deacon
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ARM: prefetch: add support for prefetchw using pldw on SMP ARMv7+ CPUs 



SMP ARMv7 CPUs implement the pldw instruction, which allows them to
prefetch data cachelines in an exclusive state.

This patch defines the prefetchw macro using pldw for CPUs that support
it.

Acked-by: default avatarNicolas Pitre <nico@linaro.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 27a84793

arch/arm/include/asm/processor.h

+12 −5
Original line number Diff line number Diff line
@@ -112,12 +112,19 @@ static inline void prefetch(const void *ptr) 
		:: "p" (ptr));

}



#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)

#define ARCH_HAS_PREFETCHW

#define prefetchw(ptr)	prefetch(ptr)



#define ARCH_HAS_SPINLOCK_PREFETCH

#define spin_lock_prefetch(x) do { } while (0)



static inline void prefetchw(const void *ptr)

{

	__asm__ __volatile__(

		".arch_extension	mp\n"

		__ALT_SMP_ASM(

			WASM(pldw)		"\t%a0",

			WASM(pld)		"\t%a0"

		)

		:: "p" (ptr));

}

#endif

#endif



#define HAVE_ARCH_PICK_MMAP_LAYOUT