Merge remote-tracking branches 'spi/topic/spidev', 'spi/topic/spidev-test',... (d8f52072) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/spi/spi-loopback-test.c

+78 −41

Original line number	Original line	Diff line number	Diff line
	@@ -20,6 +20,7 @@

	#include <linux/delay.h>		#include <linux/delay.h>
	#include <linux/kernel.h>		#include <linux/kernel.h>
			#include <linux/ktime.h>
	#include <linux/list.h>		#include <linux/list.h>
	#include <linux/list_sort.h>		#include <linux/list_sort.h>
	#include <linux/module.h>		#include <linux/module.h>
	@@ -76,9 +77,9 @@ static struct spi_test spi_tests[] = {
	.iterate_len = { ITERATE_MAX_LEN },		.iterate_len = { ITERATE_MAX_LEN },
	.iterate_tx_align = ITERATE_ALIGN,		.iterate_tx_align = ITERATE_ALIGN,
	.iterate_rx_align = ITERATE_ALIGN,		.iterate_rx_align = ITERATE_ALIGN,
			.transfer_count = 1,
	.transfers = {		.transfers = {
	{		{
	.len = 1,
	.tx_buf = TX(0),		.tx_buf = TX(0),
	.rx_buf = RX(0),		.rx_buf = RX(0),
	},		},
	@@ -90,9 +91,9 @@ static struct spi_test spi_tests[] = {
	.iterate_len = { ITERATE_MAX_LEN },		.iterate_len = { ITERATE_MAX_LEN },
	.iterate_tx_align = ITERATE_ALIGN,		.iterate_tx_align = ITERATE_ALIGN,
	.iterate_rx_align = ITERATE_ALIGN,		.iterate_rx_align = ITERATE_ALIGN,
			.transfer_count = 1,
	.transfers = {		.transfers = {
	{		{
	.len = 1,
	.tx_buf = TX(PAGE_SIZE - 4),		.tx_buf = TX(PAGE_SIZE - 4),
	.rx_buf = RX(PAGE_SIZE - 4),		.rx_buf = RX(PAGE_SIZE - 4),
	},		},
	@@ -103,9 +104,9 @@ static struct spi_test spi_tests[] = {
	.fill_option = FILL_COUNT_8,		.fill_option = FILL_COUNT_8,
	.iterate_len = { ITERATE_MAX_LEN },		.iterate_len = { ITERATE_MAX_LEN },
	.iterate_tx_align = ITERATE_ALIGN,		.iterate_tx_align = ITERATE_ALIGN,
			.transfer_count = 1,
	.transfers = {		.transfers = {
	{		{
	.len = 1,
	.tx_buf = TX(0),		.tx_buf = TX(0),
	},		},
	},		},
	@@ -115,9 +116,9 @@ static struct spi_test spi_tests[] = {
	.fill_option = FILL_COUNT_8,		.fill_option = FILL_COUNT_8,
	.iterate_len = { ITERATE_MAX_LEN },		.iterate_len = { ITERATE_MAX_LEN },
	.iterate_rx_align = ITERATE_ALIGN,		.iterate_rx_align = ITERATE_ALIGN,
			.transfer_count = 1,
	.transfers = {		.transfers = {
	{		{
	.len = 1,
	.rx_buf = RX(0),		.rx_buf = RX(0),
	},		},
	},		},
	@@ -128,13 +129,12 @@ static struct spi_test spi_tests[] = {
	.iterate_len = { ITERATE_LEN },		.iterate_len = { ITERATE_LEN },
	.iterate_tx_align = ITERATE_ALIGN,		.iterate_tx_align = ITERATE_ALIGN,
	.iterate_transfer_mask = BIT(0) \| BIT(1),		.iterate_transfer_mask = BIT(0) \| BIT(1),
			.transfer_count = 2,
	.transfers = {		.transfers = {
	{		{
	.len = 1,
	.tx_buf = TX(0),		.tx_buf = TX(0),
	},		},
	{		{
	.len = 1,
	/* this is why we cant use ITERATE_MAX_LEN */		/* this is why we cant use ITERATE_MAX_LEN */
	.tx_buf = TX(SPI_TEST_MAX_SIZE_HALF),		.tx_buf = TX(SPI_TEST_MAX_SIZE_HALF),
	},		},
	@@ -145,10 +145,10 @@ static struct spi_test spi_tests[] = {
	.fill_option = FILL_COUNT_8,		.fill_option = FILL_COUNT_8,
	.iterate_len = { ITERATE_MAX_LEN },		.iterate_len = { ITERATE_MAX_LEN },
	.iterate_tx_align = ITERATE_ALIGN,		.iterate_tx_align = ITERATE_ALIGN,
	.iterate_transfer_mask = BIT(1),		.iterate_transfer_mask = BIT(0),
			.transfer_count = 2,
	.transfers = {		.transfers = {
	{		{
	.len = 1,
	.tx_buf = TX(64),		.tx_buf = TX(64),
	},		},
	{		{
	@@ -162,14 +162,14 @@ static struct spi_test spi_tests[] = {
	.fill_option = FILL_COUNT_8,		.fill_option = FILL_COUNT_8,
	.iterate_len = { ITERATE_MAX_LEN },		.iterate_len = { ITERATE_MAX_LEN },
	.iterate_tx_align = ITERATE_ALIGN,		.iterate_tx_align = ITERATE_ALIGN,
	.iterate_transfer_mask = BIT(0),		.iterate_transfer_mask = BIT(1),
			.transfer_count = 2,
	.transfers = {		.transfers = {
	{		{
	.len = 16,		.len = 16,
	.tx_buf = TX(0),		.tx_buf = TX(0),
	},		},
	{		{
	.len = 1,
	.tx_buf = TX(64),		.tx_buf = TX(64),
	},		},
	},		},
	@@ -180,13 +180,12 @@ static struct spi_test spi_tests[] = {
	.iterate_len = { ITERATE_MAX_LEN },		.iterate_len = { ITERATE_MAX_LEN },
	.iterate_tx_align = ITERATE_ALIGN,		.iterate_tx_align = ITERATE_ALIGN,
	.iterate_transfer_mask = BIT(0) \| BIT(1),		.iterate_transfer_mask = BIT(0) \| BIT(1),
			.transfer_count = 2,
	.transfers = {		.transfers = {
	{		{
	.len = 1,
	.tx_buf = TX(0),		.tx_buf = TX(0),
	},		},
	{		{
	.len = 1,
	.rx_buf = RX(0),		.rx_buf = RX(0),
	},		},
	},		},
	@@ -197,9 +196,9 @@ static struct spi_test spi_tests[] = {
	.iterate_len = { ITERATE_MAX_LEN },		.iterate_len = { ITERATE_MAX_LEN },
	.iterate_tx_align = ITERATE_ALIGN,		.iterate_tx_align = ITERATE_ALIGN,
	.iterate_transfer_mask = BIT(0),		.iterate_transfer_mask = BIT(0),
			.transfer_count = 2,
	.transfers = {		.transfers = {
	{		{
	.len = 1,
	.tx_buf = TX(0),		.tx_buf = TX(0),
	},		},
	{		{
	@@ -214,13 +213,13 @@ static struct spi_test spi_tests[] = {
	.iterate_len = { ITERATE_MAX_LEN },		.iterate_len = { ITERATE_MAX_LEN },
	.iterate_tx_align = ITERATE_ALIGN,		.iterate_tx_align = ITERATE_ALIGN,
	.iterate_transfer_mask = BIT(1),		.iterate_transfer_mask = BIT(1),
			.transfer_count = 2,
	.transfers = {		.transfers = {
	{		{
	.len = 1,		.len = 1,
	.tx_buf = TX(0),		.tx_buf = TX(0),
	},		},
	{		{
	.len = 1,
	.rx_buf = RX(0),		.rx_buf = RX(0),
	},		},
	},		},
	@@ -231,14 +230,13 @@ static struct spi_test spi_tests[] = {
	.iterate_len = { ITERATE_LEN },		.iterate_len = { ITERATE_LEN },
	.iterate_tx_align = ITERATE_ALIGN,		.iterate_tx_align = ITERATE_ALIGN,
	.iterate_transfer_mask = BIT(0) \| BIT(1),		.iterate_transfer_mask = BIT(0) \| BIT(1),
			.transfer_count = 2,
	.transfers = {		.transfers = {
	{		{
	.len = 1,
	.tx_buf = TX(0),		.tx_buf = TX(0),
	.rx_buf = RX(0),		.rx_buf = RX(0),
	},		},
	{		{
	.len = 1,
	/* making sure we align without overwrite		/* making sure we align without overwrite
	* the reason we can not use ITERATE_MAX_LEN		* the reason we can not use ITERATE_MAX_LEN
	*/		*/
	@@ -253,9 +251,9 @@ static struct spi_test spi_tests[] = {
	.iterate_len = { ITERATE_MAX_LEN },		.iterate_len = { ITERATE_MAX_LEN },
	.iterate_tx_align = ITERATE_ALIGN,		.iterate_tx_align = ITERATE_ALIGN,
	.iterate_transfer_mask = BIT(0),		.iterate_transfer_mask = BIT(0),
			.transfer_count = 2,
	.transfers = {		.transfers = {
	{		{
	.len = 1,
	/* making sure we align without overwrite */		/* making sure we align without overwrite */
	.tx_buf = TX(1024),		.tx_buf = TX(1024),
	.rx_buf = RX(1024),		.rx_buf = RX(1024),
	@@ -274,6 +272,7 @@ static struct spi_test spi_tests[] = {
	.iterate_len = { ITERATE_MAX_LEN },		.iterate_len = { ITERATE_MAX_LEN },
	.iterate_tx_align = ITERATE_ALIGN,		.iterate_tx_align = ITERATE_ALIGN,
	.iterate_transfer_mask = BIT(1),		.iterate_transfer_mask = BIT(1),
			.transfer_count = 2,
	.transfers = {		.transfers = {
	{		{
	.len = 1,		.len = 1,
	@@ -281,13 +280,31 @@ static struct spi_test spi_tests[] = {
	.rx_buf = RX(0),		.rx_buf = RX(0),
	},		},
	{		{
	.len = 1,
	/* making sure we align without overwrite */		/* making sure we align without overwrite */
	.tx_buf = TX(1024),		.tx_buf = TX(1024),
	.rx_buf = RX(1024),		.rx_buf = RX(1024),
	},		},
	},		},
	},		},
			{
			.description = "two tx+rx transfers - delay after transfer",
			.fill_option = FILL_COUNT_8,
			.iterate_len = { ITERATE_MAX_LEN },
			.iterate_transfer_mask = BIT(0) \| BIT(1),
			.transfer_count = 2,
			.transfers = {
			{
			.tx_buf = TX(0),
			.rx_buf = RX(0),
			.delay_usecs = 1000,
			},
			{
			.tx_buf = TX(0),
			.rx_buf = RX(0),
			.delay_usecs = 1000,
			},
			},
			},

	{ /* end of tests sequence */ }		{ /* end of tests sequence */ }
	};		};
	@@ -495,6 +512,36 @@ static int spi_check_rx_ranges(struct spi_device *spi,
	return ret;		return ret;
	}		}

			static int spi_test_check_elapsed_time(struct spi_device *spi,
			struct spi_test *test)
			{
			int i;
			unsigned long long estimated_time = 0;
			unsigned long long delay_usecs = 0;

			for (i = 0; i < test->transfer_count; i++) {
			struct spi_transfer *xfer = test->transfers + i;
			unsigned long long nbits = (unsigned long long)BITS_PER_BYTE *
			xfer->len;

			delay_usecs += xfer->delay_usecs;
			if (!xfer->speed_hz)
			continue;
			estimated_time += div_u64(nbits * NSEC_PER_SEC, xfer->speed_hz);
			}

			estimated_time += delay_usecs * NSEC_PER_USEC;
			if (test->elapsed_time < estimated_time) {
			dev_err(&spi->dev,
			"elapsed time %lld ns is shorter than minimum estimated time %lld ns\n",
			test->elapsed_time, estimated_time);

			return -EINVAL;
			}

			return 0;
			}

	static int spi_test_check_loopback_result(struct spi_device *spi,		static int spi_test_check_loopback_result(struct spi_device *spi,
	struct spi_message *msg,		struct spi_message *msg,
	void tx, void rx)		void tx, void rx)
	@@ -518,11 +565,11 @@ static int spi_test_check_loopback_result(struct spi_device *spi,
	/* if applicable to transfer check that rx_buf is equal to tx_buf */		/* if applicable to transfer check that rx_buf is equal to tx_buf */
	list_for_each_entry(xfer, &msg->transfers, transfer_list) {		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
	/* if there is no rx, then no check is needed */		/* if there is no rx, then no check is needed */
	if (!xfer->rx_buf)		if (!xfer->len \|\| !xfer->rx_buf)
	continue;		continue;
	/* so depending on tx_buf we need to handle things */		/* so depending on tx_buf we need to handle things */
	if (xfer->tx_buf) {		if (xfer->tx_buf) {
	for (i = 1; i < xfer->len; i++) {		for (i = 0; i < xfer->len; i++) {
	txb = ((u8 *)xfer->tx_buf)[i];		txb = ((u8 *)xfer->tx_buf)[i];
	rxb = ((u8 *)xfer->rx_buf)[i];		rxb = ((u8 *)xfer->rx_buf)[i];
	if (txb != rxb)		if (txb != rxb)
	@@ -760,15 +807,6 @@ static int spi_test_run_iter(struct spi_device *spi,
	/* copy the test template to test */		/* copy the test template to test */
	memcpy(&test, testtemplate, sizeof(test));		memcpy(&test, testtemplate, sizeof(test));

	/* set up test->transfers to the correct count */
	if (!test.transfer_count) {
	for (i = 0;
	(i < SPI_TEST_MAX_TRANSFERS) && test.transfers[i].len;
	i++) {
	test.transfer_count++;
	}
	}

	/* if iterate_transfer_mask is not set,		/* if iterate_transfer_mask is not set,
	* then set it to first transfer only		* then set it to first transfer only
	*/		*/
	@@ -814,7 +852,6 @@ static int spi_test_run_iter(struct spi_device *spi,
	/* only when bit in transfer mask is set */		/* only when bit in transfer mask is set */
	if (!(test.iterate_transfer_mask & BIT(i)))		if (!(test.iterate_transfer_mask & BIT(i)))
	continue;		continue;
	if (len)
	test.transfers[i].len = len;		test.transfers[i].len = len;
	if (test.transfers[i].tx_buf)		if (test.transfers[i].tx_buf)
	test.transfers[i].tx_buf += tx_off;		test.transfers[i].tx_buf += tx_off;
	@@ -845,12 +882,16 @@ int spi_test_execute_msg(struct spi_device spi, struct spi_test test,

	/* only if we do not simulate */		/* only if we do not simulate */
	if (!simulate_only) {		if (!simulate_only) {
			ktime_t start;

	/* dump the complete message before and after the transfer */		/* dump the complete message before and after the transfer */
	if (dump_messages == 3)		if (dump_messages == 3)
	spi_test_dump_message(spi, msg, true);		spi_test_dump_message(spi, msg, true);

			start = ktime_get();
	/* run spi message */		/* run spi message */
	ret = spi_sync(spi, msg);		ret = spi_sync(spi, msg);
			test->elapsed_time = ktime_to_ns(ktime_sub(ktime_get(), start));
	if (ret == -ETIMEDOUT) {		if (ret == -ETIMEDOUT) {
	dev_info(&spi->dev,		dev_info(&spi->dev,
	"spi-message timed out - reruning...\n");		"spi-message timed out - reruning...\n");
	@@ -876,6 +917,10 @@ int spi_test_execute_msg(struct spi_device spi, struct spi_test test,

	/* run rx-buffer tests */		/* run rx-buffer tests */
	ret = spi_test_check_loopback_result(spi, msg, tx, rx);		ret = spi_test_check_loopback_result(spi, msg, tx, rx);
			if (ret)
			goto exit;

			ret = spi_test_check_elapsed_time(spi, test);
	}		}

	/* if requested or on error dump message (including data) */		/* if requested or on error dump message (including data) */
	@@ -925,15 +970,6 @@ int spi_test_run_test(struct spi_device spi, const struct spi_test test,
	/* iterate over all the iterable values using macros		/* iterate over all the iterable values using macros
	* (to make it a bit more readable...		* (to make it a bit more readable...
	*/		*/
	#define FOR_EACH_ITERATE(var, defaultvalue) \
	for (idx_##var = -1, var = defaultvalue; \
	((idx_##var < 0) \|\| \
	( \
	(idx_##var < SPI_TEST_MAX_ITERATE) && \
	(var = test->iterate_##var[idx_##var]) \
	) \
	); \
	idx_##var++)
	#define FOR_EACH_ALIGNMENT(var) \		#define FOR_EACH_ALIGNMENT(var) \
	for (var = 0; \		for (var = 0; \
	var < (test->iterate_##var ? \		var < (test->iterate_##var ? \
	@@ -943,7 +979,8 @@ int spi_test_run_test(struct spi_device spi, const struct spi_test test,
	1); \		1); \
	var++)		var++)

	FOR_EACH_ITERATE(len, 0) {		for (idx_len = 0; idx_len < SPI_TEST_MAX_ITERATE &&
			(len = test->iterate_len[idx_len]) != -1; idx_len++) {
	FOR_EACH_ALIGNMENT(tx_align) {		FOR_EACH_ALIGNMENT(tx_align) {
	FOR_EACH_ALIGNMENT(rx_align) {		FOR_EACH_ALIGNMENT(rx_align) {
	/* and run the iteration */		/* and run the iteration */

drivers/spi/spi-sun6i.c

+82 −12

Original line number	Original line	Diff line number	Diff line
	@@ -46,13 +46,19 @@
	#define SUN6I_TFR_CTL_XCH BIT(31)		#define SUN6I_TFR_CTL_XCH BIT(31)

	#define SUN6I_INT_CTL_REG 0x10		#define SUN6I_INT_CTL_REG 0x10
			#define SUN6I_INT_CTL_RF_RDY BIT(0)
			#define SUN6I_INT_CTL_TF_ERQ BIT(4)
	#define SUN6I_INT_CTL_RF_OVF BIT(8)		#define SUN6I_INT_CTL_RF_OVF BIT(8)
	#define SUN6I_INT_CTL_TC BIT(12)		#define SUN6I_INT_CTL_TC BIT(12)

	#define SUN6I_INT_STA_REG 0x14		#define SUN6I_INT_STA_REG 0x14

	#define SUN6I_FIFO_CTL_REG 0x18		#define SUN6I_FIFO_CTL_REG 0x18
			#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
			#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
	#define SUN6I_FIFO_CTL_RF_RST BIT(15)		#define SUN6I_FIFO_CTL_RF_RST BIT(15)
			#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
			#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
	#define SUN6I_FIFO_CTL_TF_RST BIT(31)		#define SUN6I_FIFO_CTL_TF_RST BIT(31)

	#define SUN6I_FIFO_STA_REG 0x1c		#define SUN6I_FIFO_STA_REG 0x1c
	@@ -68,14 +74,16 @@
	#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)		#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
	#define SUN6I_CLK_CTL_DRS BIT(12)		#define SUN6I_CLK_CTL_DRS BIT(12)

			#define SUN6I_MAX_XFER_SIZE 0xffffff

	#define SUN6I_BURST_CNT_REG 0x30		#define SUN6I_BURST_CNT_REG 0x30
	#define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff)		#define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)

	#define SUN6I_XMIT_CNT_REG 0x34		#define SUN6I_XMIT_CNT_REG 0x34
	#define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff)		#define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)

	#define SUN6I_BURST_CTL_CNT_REG 0x38		#define SUN6I_BURST_CTL_CNT_REG 0x38
	#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff)		#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)

	#define SUN6I_TXDATA_REG 0x200		#define SUN6I_TXDATA_REG 0x200
	#define SUN6I_RXDATA_REG 0x300		#define SUN6I_RXDATA_REG 0x300
	@@ -105,6 +113,31 @@ static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
	writel(value, sspi->base_addr + reg);		writel(value, sspi->base_addr + reg);
	}		}

			static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
			{
			u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);

			reg >>= SUN6I_FIFO_STA_TF_CNT_BITS;

			return reg & SUN6I_FIFO_STA_TF_CNT_MASK;
			}

			static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask)
			{
			u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);

			reg \|= mask;
			sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
			}

			static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
			{
			u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);

			reg &= ~mask;
			sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
			}

	static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)		static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
	{		{
	u32 reg, cnt;		u32 reg, cnt;
	@@ -127,10 +160,13 @@ static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)

	static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)		static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
	{		{
			u32 cnt;
	u8 byte;		u8 byte;

	if (len > sspi->len)		/* See how much data we can fit */
	len = sspi->len;		cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);

			len = min3(len, (int)cnt, sspi->len);

	while (len--) {		while (len--) {
	byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;		byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
	@@ -158,9 +194,7 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)

	static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)		static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
	{		{
	struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);		return SUN6I_MAX_XFER_SIZE - 1;

	return sspi->fifo_depth - 1;
	}		}

	static int sun6i_spi_transfer_one(struct spi_master *master,		static int sun6i_spi_transfer_one(struct spi_master *master,
	@@ -170,12 +204,12 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
	struct sun6i_spi *sspi = spi_master_get_devdata(master);		struct sun6i_spi *sspi = spi_master_get_devdata(master);
	unsigned int mclk_rate, div, timeout;		unsigned int mclk_rate, div, timeout;
	unsigned int start, end, tx_time;		unsigned int start, end, tx_time;
			unsigned int trig_level;
	unsigned int tx_len = 0;		unsigned int tx_len = 0;
	int ret = 0;		int ret = 0;
	u32 reg;		u32 reg;

	/* We don't support transfer larger than the FIFO */		if (tfr->len > SUN6I_MAX_XFER_SIZE)
	if (tfr->len > sspi->fifo_depth)
	return -EINVAL;		return -EINVAL;

	reinit_completion(&sspi->done);		reinit_completion(&sspi->done);
	@@ -190,6 +224,17 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
	sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,		sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
	SUN6I_FIFO_CTL_RF_RST \| SUN6I_FIFO_CTL_TF_RST);		SUN6I_FIFO_CTL_RF_RST \| SUN6I_FIFO_CTL_TF_RST);

			/*
			* Setup FIFO interrupt trigger level
			* Here we choose 3/4 of the full fifo depth, as it's the hardcoded
			* value used in old generation of Allwinner SPI controller.
			* (See spi-sun4i.c)
			*/
			trig_level = sspi->fifo_depth / 4 * 3;
			sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
			(trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) \|
			(trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));

	/*		/*
	* Setup the transfer control register: Chip Select,		* Setup the transfer control register: Chip Select,
	* polarities, etc.		* polarities, etc.
	@@ -274,6 +319,10 @@ static int sun6i_spi_transfer_one(struct spi_master *master,

	/* Enable the interrupts */		/* Enable the interrupts */
	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);		sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
			sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC \|
			SUN6I_INT_CTL_RF_RDY);
			if (tx_len > sspi->fifo_depth)
			sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);

	/* Start the transfer */		/* Start the transfer */
	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);		reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
	@@ -293,8 +342,6 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
	goto out;		goto out;
	}		}

	sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);

	out:		out:
	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);		sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);

	@@ -309,10 +356,33 @@ static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
	/* Transfer complete */		/* Transfer complete */
	if (status & SUN6I_INT_CTL_TC) {		if (status & SUN6I_INT_CTL_TC) {
	sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
			sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
	complete(&sspi->done);		complete(&sspi->done);
	return IRQ_HANDLED;		return IRQ_HANDLED;
	}		}

			/* Receive FIFO 3/4 full */
			if (status & SUN6I_INT_CTL_RF_RDY) {
			sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
			/* Only clear the interrupt _after_ draining the FIFO */
			sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
			return IRQ_HANDLED;
			}

			/* Transmit FIFO 3/4 empty */
			if (status & SUN6I_INT_CTL_TF_ERQ) {
			sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);

			if (!sspi->len)
			/* nothing left to transmit */
			sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);

			/* Only clear the interrupt _after_ re-seeding the FIFO */
			sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);

			return IRQ_HANDLED;
			}

	return IRQ_NONE;		return IRQ_NONE;
	}		}

drivers/spi/spi-tegra114.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -837,7 +837,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
	SPI_DMA_TIMEOUT);		SPI_DMA_TIMEOUT);
	if (WARN_ON(ret == 0)) {		if (WARN_ON(ret == 0)) {
	dev_err(tspi->dev,		dev_err(tspi->dev,
	"spi trasfer timeout, err %d\n", ret);		"spi transfer timeout, err %d\n", ret);
	ret = -EIO;		ret = -EIO;
	goto complete_xfer;		goto complete_xfer;
	}		}

drivers/spi/spi-tegra20-sflash.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -341,7 +341,7 @@ static int tegra_sflash_transfer_one_message(struct spi_master *master,
	SPI_DMA_TIMEOUT);		SPI_DMA_TIMEOUT);
	if (WARN_ON(ret == 0)) {		if (WARN_ON(ret == 0)) {
	dev_err(tsd->dev,		dev_err(tsd->dev,
	"spi trasfer timeout, err %d\n", ret);		"spi transfer timeout, err %d\n", ret);
	ret = -EIO;		ret = -EIO;
	goto exit;		goto exit;
	}		}

drivers/spi/spi-tegra20-slink.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -824,7 +824,7 @@ static int tegra_slink_transfer_one(struct spi_master *master,
	SLINK_DMA_TIMEOUT);		SLINK_DMA_TIMEOUT);
	if (WARN_ON(ret == 0)) {		if (WARN_ON(ret == 0)) {
	dev_err(tspi->dev,		dev_err(tspi->dev,
	"spi trasfer timeout, err %d\n", ret);		"spi transfer timeout, err %d\n", ret);
	return -EIO;		return -EIO;
	}		}