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Commit d8dd6804 authored by Haneen Mohammed's avatar Haneen Mohammed Committed by Mark Yao
Browse files

drm/rockchip: Replace dev_* with DRM_DEV_* 



This patch replace instances of dev_info/err/debug with
DRM_DEV_INFO/ERROR/WARN respectively inorder to use a drm-formatted
specific log messages. Issue corrected with the help of the following
Coccinelle script:

@r@
@@

(
-dev_info
+DRM_DEV_INFO
|
-dev_err
+DRM_DEV_ERROR
|
-dev_dbg
+DRM_DEV_DEBUG
)

Signed-off-by: default avatarHaneen Mohammed <hamohammed.sa@gmail.com>
Signed-off-by: default avatarMark Yao <mark.yao@rock-chips.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170915083603.GA18992@Haneen
parent 95a0cfe9

drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

+13 −13
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled) 
	if (!analogix_dp_psr_supported(dp->dev))

		return;



	dev_dbg(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");

	DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");



	spin_lock_irqsave(&dp->psr_lock, flags);

	if (enabled)
@@ -110,7 +110,7 @@ static void analogix_dp_psr_work(struct work_struct *work) 
	ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,

					 PSR_WAIT_LINE_FLAG_TIMEOUT_MS);

	if (ret) {

		dev_err(dp->dev, "line flag interrupt did not arrive\n");

		DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n");

		return;

	}
@@ -140,13 +140,13 @@ static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data) 


	ret = clk_prepare_enable(dp->pclk);

	if (ret < 0) {

		dev_err(dp->dev, "failed to enable pclk %d\n", ret);

		DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);

		return ret;

	}



	ret = rockchip_dp_pre_init(dp);

	if (ret < 0) {

		dev_err(dp->dev, "failed to dp pre init %d\n", ret);

		DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);

		clk_disable_unprepare(dp->pclk);

		return ret;

	}
@@ -211,17 +211,17 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder) 
	else

		val = dp->data->lcdsel_big;



	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");

	DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");



	ret = clk_prepare_enable(dp->grfclk);

	if (ret < 0) {

		dev_err(dp->dev, "failed to enable grfclk %d\n", ret);

		DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);

		return;

	}



	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);

	if (ret != 0)

		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);

		DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);



	clk_disable_unprepare(dp->grfclk);

}
@@ -277,7 +277,7 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp) 


	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");

	if (IS_ERR(dp->grf)) {

		dev_err(dev, "failed to get rockchip,grf property\n");

		DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");

		return PTR_ERR(dp->grf);

	}
@@ -287,31 +287,31 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp) 
	} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {

		return -EPROBE_DEFER;

	} else if (IS_ERR(dp->grfclk)) {

		dev_err(dev, "failed to get grf clock\n");

		DRM_DEV_ERROR(dev, "failed to get grf clock\n");

		return PTR_ERR(dp->grfclk);

	}



	dp->pclk = devm_clk_get(dev, "pclk");

	if (IS_ERR(dp->pclk)) {

		dev_err(dev, "failed to get pclk property\n");

		DRM_DEV_ERROR(dev, "failed to get pclk property\n");

		return PTR_ERR(dp->pclk);

	}



	dp->rst = devm_reset_control_get(dev, "dp");

	if (IS_ERR(dp->rst)) {

		dev_err(dev, "failed to get dp reset control\n");

		DRM_DEV_ERROR(dev, "failed to get dp reset control\n");

		return PTR_ERR(dp->rst);

	}



	ret = clk_prepare_enable(dp->pclk);

	if (ret < 0) {

		dev_err(dp->dev, "failed to enable pclk %d\n", ret);

		DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);

		return ret;

	}



	ret = rockchip_dp_pre_init(dp);

	if (ret < 0) {

		dev_err(dp->dev, "failed to pre init %d\n", ret);

		DRM_DEV_ERROR(dp->dev, "failed to pre init %d\n", ret);

		clk_disable_unprepare(dp->pclk);

		return ret;

	}

drivers/gpu/drm/rockchip/cdn-dp-reg.c

+1 −1
Original line number Diff line number Diff line
@@ -323,7 +323,7 @@ int cdn_dp_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem, 
	reg = readl(dp->regs + VER_LIB_H_ADDR) & 0xff;

	dp->fw_version |= reg << 24;



	dev_dbg(dp->dev, "firmware version: %x\n", dp->fw_version);

	DRM_DEV_DEBUG(dp->dev, "firmware version: %x\n", dp->fw_version);



	return 0;

}

drivers/gpu/drm/rockchip/dw-mipi-dsi.c

+48 −38
Original line number Diff line number Diff line
@@ -430,7 +430,7 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 


	testdin = max_mbps_to_testdin(dsi->lane_mbps);

	if (testdin < 0) {

		dev_err(dsi->dev,

		DRM_DEV_ERROR(dsi->dev,

			      "failed to get testdin for %dmbps lane clock\n",

			      dsi->lane_mbps);

		return testdin;
@@ -443,7 +443,7 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 


	ret = clk_prepare_enable(dsi->phy_cfg_clk);

	if (ret) {

		dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");

		DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");

		return ret;

	}
@@ -501,7 +501,7 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 
	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,

				 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);

	if (ret < 0) {

		dev_err(dsi->dev, "failed to wait for phy lock state\n");

		DRM_DEV_ERROR(dsi->dev, "failed to wait for phy lock state\n");

		goto phy_init_end;

	}
@@ -509,7 +509,7 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) 
				 val, val & STOP_STATE_CLK_LANE, 1000,

				 PHY_STATUS_TIMEOUT_US);

	if (ret < 0)

		dev_err(dsi->dev,

		DRM_DEV_ERROR(dsi->dev,

			      "failed to wait for phy clk lane stop state\n");



phy_init_end:
@@ -529,7 +529,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, 


	bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);

	if (bpp < 0) {

		dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",

		DRM_DEV_ERROR(dsi->dev,

			      "failed to get bpp for pixel format %d\n",

			      dsi->format);

		return bpp;

	}
@@ -541,7 +542,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, 
		if (tmp < max_mbps)

			target_mbps = tmp;

		else

			dev_err(dsi->dev, "DPHY clock frequency is out of range\n");

			DRM_DEV_ERROR(dsi->dev,

				      "DPHY clock frequency is out of range\n");

	}



	pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
@@ -582,7 +584,8 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 
	struct dw_mipi_dsi *dsi = host_to_dsi(host);



	if (device->lanes > dsi->pdata->max_data_lanes) {

		dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",

		DRM_DEV_ERROR(dsi->dev,

			      "the number of data lanes(%u) is too many\n",

			      device->lanes);

		return -EINVAL;

	}
@@ -632,7 +635,8 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) 
				 val, !(val & GEN_CMD_FULL), 1000,

				 CMD_PKT_STATUS_TIMEOUT_US);

	if (ret < 0) {

		dev_err(dsi->dev, "failed to get available command FIFO\n");

		DRM_DEV_ERROR(dsi->dev,

			      "failed to get available command FIFO\n");

		return ret;

	}
@@ -643,7 +647,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) 
				 val, (val & mask) == mask,

				 1000, CMD_PKT_STATUS_TIMEOUT_US);

	if (ret < 0) {

		dev_err(dsi->dev, "failed to write command FIFO\n");

		DRM_DEV_ERROR(dsi->dev, "failed to write command FIFO\n");

		return ret;

	}
@@ -663,7 +667,8 @@ static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi, 
		data |= tx_buf[1] << 8;



	if (msg->tx_len > 2) {

		dev_err(dsi->dev, "too long tx buf length %zu for short write\n",

		DRM_DEV_ERROR(dsi->dev,

			      "too long tx buf length %zu for short write\n",

			      msg->tx_len);

		return -EINVAL;

	}
@@ -682,7 +687,8 @@ static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi, 
	u32 val;



	if (msg->tx_len < 3) {

		dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",

		DRM_DEV_ERROR(dsi->dev,

			      "wrong tx buf length %zu for long write\n",

			      msg->tx_len);

		return -EINVAL;

	}
@@ -704,7 +710,7 @@ static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi, 
					 val, !(val & GEN_PLD_W_FULL), 1000,

					 CMD_PKT_STATUS_TIMEOUT_US);

		if (ret < 0) {

			dev_err(dsi->dev,

			DRM_DEV_ERROR(dsi->dev,

				      "failed to get available write payload FIFO\n");

			return ret;

		}
@@ -731,7 +737,7 @@ static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 
		ret = dw_mipi_dsi_dcs_long_write(dsi, msg);

		break;

	default:

		dev_err(dsi->dev, "unsupported message type 0x%02x\n",

		DRM_DEV_ERROR(dsi->dev, "unsupported message type 0x%02x\n",

			      msg->type);

		ret = -EINVAL;

	}
@@ -935,7 +941,7 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder) 
		return;



	if (clk_prepare_enable(dsi->pclk)) {

		dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);

		DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk\n");

		return;

	}
@@ -967,7 +973,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 
		return;



	if (clk_prepare_enable(dsi->pclk)) {

		dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);

		DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk\n");

		return;

	}
@@ -991,7 +997,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 
	 */

	ret = clk_prepare_enable(dsi->grf_clk);

	if (ret) {

		dev_err(dsi->dev, "Failed to enable grf_clk: %d\n", ret);

		DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);

		return;

	}
@@ -1004,7 +1010,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 


	dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);

	if (drm_panel_prepare(dsi->panel))

		dev_err(dsi->dev, "failed to prepare panel\n");

		DRM_DEV_ERROR(dsi->dev, "failed to prepare panel\n");



	dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);

	drm_panel_enable(dsi->panel);
@@ -1017,7 +1023,8 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 
		val = pdata->dsi0_en_bit << 16;



	regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);

	dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");

	DRM_DEV_DEBUG(dsi->dev,

		      "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");

	dsi->dpms_mode = DRM_MODE_DPMS_ON;



	clk_disable_unprepare(dsi->grf_clk);
@@ -1111,7 +1118,7 @@ static int dw_mipi_dsi_register(struct drm_device *drm, 
	ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,

			       DRM_MODE_ENCODER_DSI, NULL);

	if (ret) {

		dev_err(dev, "Failed to initialize encoder with drm\n");

		DRM_DEV_ERROR(dev, "Failed to initialize encoder with drm\n");

		return ret;

	}
@@ -1133,7 +1140,7 @@ static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi) 


	dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");

	if (IS_ERR(dsi->grf_regmap)) {

		dev_err(dsi->dev, "Unable to get rockchip,grf\n");

		DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");

		return PTR_ERR(dsi->grf_regmap);

	}
@@ -1205,14 +1212,15 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, 
	dsi->pllref_clk = devm_clk_get(dev, "ref");

	if (IS_ERR(dsi->pllref_clk)) {

		ret = PTR_ERR(dsi->pllref_clk);

		dev_err(dev, "Unable to get pll reference clock: %d\n", ret);

		DRM_DEV_ERROR(dev,

			      "Unable to get pll reference clock: %d\n", ret);

		return ret;

	}



	dsi->pclk = devm_clk_get(dev, "pclk");

	if (IS_ERR(dsi->pclk)) {

		ret = PTR_ERR(dsi->pclk);

		dev_err(dev, "Unable to get pclk: %d\n", ret);

		DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);

		return ret;

	}
@@ -1226,7 +1234,8 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, 
		if (ret == -ENOENT) {

			apb_rst = NULL;

		} else {

			dev_err(dev, "Unable to get reset control: %d\n", ret);

			DRM_DEV_ERROR(dev,

				      "Unable to get reset control: %d\n", ret);

			return ret;

		}

	}
@@ -1234,7 +1243,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, 
	if (apb_rst) {

		ret = clk_prepare_enable(dsi->pclk);

		if (ret) {

			dev_err(dev, "%s: Failed to enable pclk\n", __func__);

			DRM_DEV_ERROR(dev, "Failed to enable pclk\n");

			return ret;

		}
@@ -1249,7 +1258,8 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, 
		dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");

		if (IS_ERR(dsi->phy_cfg_clk)) {

			ret = PTR_ERR(dsi->phy_cfg_clk);

			dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);

			DRM_DEV_ERROR(dev,

				      "Unable to get phy_cfg_clk: %d\n", ret);

			return ret;

		}

	}
@@ -1258,20 +1268,20 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, 
		dsi->grf_clk = devm_clk_get(dev, "grf");

		if (IS_ERR(dsi->grf_clk)) {

			ret = PTR_ERR(dsi->grf_clk);

			dev_err(dev, "Unable to get grf_clk: %d\n", ret);

			DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);

			return ret;

		}

	}



	ret = clk_prepare_enable(dsi->pllref_clk);

	if (ret) {

		dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);

		DRM_DEV_ERROR(dev, "Failed to enable pllref_clk\n");

		return ret;

	}



	ret = dw_mipi_dsi_register(drm, dsi);

	if (ret) {

		dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);

		DRM_DEV_ERROR(dev, "Failed to register mipi_dsi: %d\n", ret);

		goto err_pllref;

	}
@@ -1281,7 +1291,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, 
	dsi->dsi_host.dev = dev;

	ret = mipi_dsi_host_register(&dsi->dsi_host);

	if (ret) {

		dev_err(dev, "Failed to register MIPI host: %d\n", ret);

		DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);

		goto err_cleanup;

	}

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

+10 −9
Original line number Diff line number Diff line
@@ -168,7 +168,7 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) 


	hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");

	if (IS_ERR(hdmi->regmap)) {

		dev_err(hdmi->dev, "Unable to get rockchip,grf\n");

		DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n");

		return PTR_ERR(hdmi->regmap);

	}
@@ -178,7 +178,7 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) 
	} else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {

		return -EPROBE_DEFER;

	} else if (IS_ERR(hdmi->vpll_clk)) {

		dev_err(hdmi->dev, "failed to get grf clock\n");

		DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");

		return PTR_ERR(hdmi->vpll_clk);

	}
@@ -188,13 +188,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) 
	} else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {

		return -EPROBE_DEFER;

	} else if (IS_ERR(hdmi->grf_clk)) {

		dev_err(hdmi->dev, "failed to get grf clock\n");

		DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");

		return PTR_ERR(hdmi->grf_clk);

	}



	ret = clk_prepare_enable(hdmi->vpll_clk);

	if (ret) {

		dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);

		DRM_DEV_ERROR(hdmi->dev,

			      "Failed to enable HDMI vpll: %d\n", ret);

		return ret;

	}
@@ -259,16 +260,16 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) 


	ret = clk_prepare_enable(hdmi->grf_clk);

	if (ret < 0) {

		dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret);

		DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret);

		return;

	}



	ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);

	if (ret != 0)

		dev_err(hdmi->dev, "Could not write to GRF: %d\n", ret);

		DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret);



	clk_disable_unprepare(hdmi->grf_clk);

	dev_dbg(hdmi->dev, "vop %s output to hdmi\n",

	DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n",

		      ret ? "LIT" : "BIG");

}
@@ -368,7 +369,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, 


	ret = rockchip_hdmi_parse_dt(hdmi);

	if (ret) {

		dev_err(hdmi->dev, "Unable to parse OF data\n");

		DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n");

		return ret;

	}

drivers/gpu/drm/rockchip/inno_hdmi.c

+8 −6
Original line number Diff line number Diff line
@@ -224,7 +224,7 @@ static void inno_hdmi_set_pwr_mode(struct inno_hdmi *hdmi, int mode) 
		break;



	default:

		dev_err(hdmi->dev, "Unknown power mode %d\n", mode);

		DRM_DEV_ERROR(hdmi->dev, "Unknown power mode %d\n", mode);

	}

}
@@ -742,7 +742,8 @@ static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap, 
	hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);



	for (i = 0; i < num; i++) {

		dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",

		DRM_DEV_DEBUG(hdmi->dev,

			      "xfer: num: %d/%d, len: %d, flags: %#x\n",

			      i + 1, num, msgs[i].len, msgs[i].flags);



		if (msgs[i].flags & I2C_M_RD)
@@ -806,7 +807,7 @@ static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi) 


	hdmi->i2c = i2c;



	dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);

	DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name);



	return adap;

}
@@ -838,13 +839,14 @@ static int inno_hdmi_bind(struct device *dev, struct device *master, 


	hdmi->pclk = devm_clk_get(hdmi->dev, "pclk");

	if (IS_ERR(hdmi->pclk)) {

		dev_err(hdmi->dev, "Unable to get HDMI pclk clk\n");

		DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI pclk clk\n");

		return PTR_ERR(hdmi->pclk);

	}



	ret = clk_prepare_enable(hdmi->pclk);

	if (ret) {

		dev_err(hdmi->dev, "Cannot enable HDMI pclk clock: %d\n", ret);

		DRM_DEV_ERROR(hdmi->dev,

			      "Cannot enable HDMI pclk clock: %d\n", ret);

		return ret;

	}