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Commit d89e2cf7 authored by Xiaowen Wu's avatar Xiaowen Wu Committed by Tatenda Chipeperekwa
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drm/msm/dp: Add P/N swap support for dp phy 



Add P/N swap support for DP PHY.

Change-Id: Ibc8be5aba9b658c52985dcd147cb2acfec9a1cf0
Signed-off-by: default avatarXiaowen Wu <wxiaowen@codeaurora.org>
Signed-off-by: default avatarTatenda Chipeperekwa <tatendac@codeaurora.org>
parent 0aa44867

drivers/gpu/drm/msm/dp/dp_catalog.c

+25 −0
Original line number Diff line number Diff line
@@ -882,6 +882,30 @@ static void dp_catalog_ctrl_lane_mapping(struct dp_catalog_ctrl *ctrl, 
			0xe4);

}



static void dp_catalog_ctrl_lane_pnswap(struct dp_catalog_ctrl *ctrl,

						u8 ln_pnswap)

{

	struct dp_catalog_private *catalog;

	struct dp_io_data *io_data;

	u32 cfg0, cfg1;



	catalog = dp_catalog_get_priv(ctrl);



	cfg0 = 0x0a;

	cfg1 = 0x0a;



	cfg0 |= ((ln_pnswap >> 0) & 0x1) << 0;

	cfg0 |= ((ln_pnswap >> 1) & 0x1) << 2;

	cfg1 |= ((ln_pnswap >> 2) & 0x1) << 0;

	cfg1 |= ((ln_pnswap >> 3) & 0x1) << 2;



	io_data = catalog->io.dp_ln_tx0;

	dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV, cfg0);



	io_data = catalog->io.dp_ln_tx1;

	dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV, cfg1);

}



static void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog_ctrl *ctrl,

						bool enable)

{
@@ -2509,6 +2533,7 @@ struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_parser *parser) 
		.state_ctrl     = dp_catalog_ctrl_state_ctrl,

		.config_ctrl    = dp_catalog_ctrl_config_ctrl,

		.lane_mapping   = dp_catalog_ctrl_lane_mapping,

		.lane_pnswap    = dp_catalog_ctrl_lane_pnswap,

		.mainlink_ctrl  = dp_catalog_ctrl_mainlink_ctrl,

		.set_pattern    = dp_catalog_ctrl_set_pattern,

		.reset          = dp_catalog_ctrl_reset,

drivers/gpu/drm/msm/dp/dp_catalog.h

+14 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

<<<<<<< HEAD

=======

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

>>>>>>> aacf58a... drm/msm/dp: Add P/N swap support for dp phy

 */



#ifndef _DP_CATALOG_H_
@@ -93,6 +106,7 @@ struct dp_catalog_ctrl { 
	void (*config_ctrl)(struct dp_catalog_ctrl *ctrl, u8 ln_cnt);

	void (*lane_mapping)(struct dp_catalog_ctrl *ctrl, bool flipped,

				char *lane_map);

	void (*lane_pnswap)(struct dp_catalog_ctrl *ctrl, u8 ln_pnswap);

	void (*mainlink_ctrl)(struct dp_catalog_ctrl *ctrl, bool enable);

	void (*set_pattern)(struct dp_catalog_ctrl *ctrl, u32 pattern);

	void (*reset)(struct dp_catalog_ctrl *ctrl);

drivers/gpu/drm/msm/dp/dp_catalog_v420.c

+25 −0
Original line number Diff line number Diff line
@@ -266,6 +266,30 @@ static void dp_catalog_ctrl_update_vx_px_v420(struct dp_catalog_ctrl *ctrl, 
	}

}



static void dp_catalog_ctrl_lane_pnswap_v420(struct dp_catalog_ctrl *ctrl,

						u8 ln_pnswap)

{

	struct dp_catalog_private_v420 *catalog;

	struct dp_io_data *io_data;

	u32 cfg0, cfg1;



	catalog = dp_catalog_get_priv_v420(ctrl);



	cfg0 = 0x0a;

	cfg1 = 0x0a;



	cfg0 |= ((ln_pnswap >> 0) & 0x1) << 0;

	cfg0 |= ((ln_pnswap >> 1) & 0x1) << 2;

	cfg1 |= ((ln_pnswap >> 2) & 0x1) << 0;

	cfg1 |= ((ln_pnswap >> 3) & 0x1) << 2;



	io_data = catalog->io->dp_ln_tx0;

	dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV_V420, cfg0);



	io_data = catalog->io->dp_ln_tx1;

	dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV_V420, cfg1);

}



static void dp_catalog_put_v420(struct dp_catalog *catalog)

{

	struct dp_catalog_private_v420 *catalog_priv;
@@ -316,6 +340,7 @@ int dp_catalog_get_v420(struct device *dev, struct dp_catalog *catalog, 
	catalog->panel.config_msa  = dp_catalog_panel_config_msa_v420;

	catalog->ctrl.phy_lane_cfg = dp_catalog_ctrl_phy_lane_cfg_v420;

	catalog->ctrl.update_vx_px = dp_catalog_ctrl_update_vx_px_v420;

	catalog->ctrl.lane_pnswap = dp_catalog_ctrl_lane_pnswap_v420;



	/* Set the default execution mode to hardware mode */

	dp_catalog_set_exe_mode_v420(catalog, "hw");

drivers/gpu/drm/msm/dp/dp_ctrl.c

+2 −0
Original line number Diff line number Diff line
@@ -161,6 +161,8 @@ static void dp_ctrl_configure_source_link_params(struct dp_ctrl_private *ctrl, 
	if (enable) {

		ctrl->catalog->lane_mapping(ctrl->catalog, ctrl->orientation,

						ctrl->parser->l_map);

		ctrl->catalog->lane_pnswap(ctrl->catalog,

						ctrl->parser->l_pnswap);

		ctrl->catalog->mst_config(ctrl->catalog, ctrl->mst_mode);

		ctrl->catalog->config_ctrl(ctrl->catalog,

				ctrl->link->link_params.lane_count);

drivers/gpu/drm/msm/dp/dp_parser.c

+6 −0
Original line number Diff line number Diff line
@@ -151,6 +151,12 @@ static int dp_parser_misc(struct dp_parser *parser) 
			parser->l_map[i] = data[i];

	}



	data = of_get_property(of_node, "qcom,pn-swap-lane-map", &len);

	if (data && (len == DP_MAX_PHY_LN)) {

		for (i = 0; i < len; i++)

			parser->l_pnswap |= (data[i] & 0x01) << i;

	}



	rc = of_property_read_u32(of_node,

		"qcom,max-pclk-frequency-khz", &parser->max_pclk_khz);

	if (rc)