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Commit d839c60a authored by Paul Cercueil's avatar Paul Cercueil Committed by Alexandre Belloni
Browse files

MIPS: jz4740: Remove obsolete code 



This commit removes two things:
- The platform_device that corresponds to the RTC driver, since we now
  probe this driver from devicetree;
- The platform power-off code, since all the jz4740-based platforms are
  now using the jz4740-rtc driver as the system power controller.

Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
Acked-by: default avatarMaarten ter Huurne <maarten@treewalker.org>
Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
parent 6ab59018

arch/mips/include/asm/mach-jz4740/platform.h

+0 −1
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ 
extern struct platform_device jz4740_udc_device;

extern struct platform_device jz4740_udc_xceiv_device;

extern struct platform_device jz4740_mmc_device;

extern struct platform_device jz4740_rtc_device;

extern struct platform_device jz4740_i2c_device;

extern struct platform_device jz4740_nand_device;

extern struct platform_device jz4740_framebuffer_device;

arch/mips/jz4740/platform.c

+0 −21
Original line number Diff line number Diff line
@@ -88,27 +88,6 @@ struct platform_device jz4740_mmc_device = { 
	.resource	= jz4740_mmc_resources,

};



/* RTC controller */

static struct resource jz4740_rtc_resources[] = {

	{

		.start	= JZ4740_RTC_BASE_ADDR,

		.end	= JZ4740_RTC_BASE_ADDR + 0x38 - 1,

		.flags	= IORESOURCE_MEM,

	},

	{

		.start	= JZ4740_IRQ_RTC,

		.end	= JZ4740_IRQ_RTC,

		.flags	= IORESOURCE_IRQ,

	},

};



struct platform_device jz4740_rtc_device = {

	.name		= "jz4740-rtc",

	.id		= -1,

	.num_resources	= ARRAY_SIZE(jz4740_rtc_resources),

	.resource	= jz4740_rtc_resources,

};



/* I2C controller */

static struct resource jz4740_i2c_resources[] = {

	{

arch/mips/jz4740/reset.c

+0 −63
Original line number Diff line number Diff line
@@ -57,71 +57,8 @@ static void jz4740_restart(char *command) 
	jz4740_halt();

}



#define JZ_REG_RTC_CTRL			0x00

#define JZ_REG_RTC_HIBERNATE		0x20

#define JZ_REG_RTC_WAKEUP_FILTER	0x24

#define JZ_REG_RTC_RESET_COUNTER	0x28



#define JZ_RTC_CTRL_WRDY		BIT(7)

#define JZ_RTC_WAKEUP_FILTER_MASK	0x0000FFE0

#define JZ_RTC_RESET_COUNTER_MASK	0x00000FE0



static inline void jz4740_rtc_wait_ready(void __iomem *rtc_base)

{

	uint32_t ctrl;



	do {

		ctrl = readl(rtc_base + JZ_REG_RTC_CTRL);

	} while (!(ctrl & JZ_RTC_CTRL_WRDY));

}



static void jz4740_power_off(void)

{

	void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x38);

	unsigned long wakeup_filter_ticks;

	unsigned long reset_counter_ticks;

	struct clk *rtc_clk;

	unsigned long rtc_rate;



	rtc_clk = clk_get(NULL, "rtc");

	if (IS_ERR(rtc_clk))

		panic("unable to get RTC clock");

	rtc_rate = clk_get_rate(rtc_clk);

	clk_put(rtc_clk);



	/*

	 * Set minimum wakeup pin assertion time: 100 ms.

	 * Range is 0 to 2 sec if RTC is clocked at 32 kHz.

	 */

	wakeup_filter_ticks = (100 * rtc_rate) / 1000;

	if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)

		wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;

	else

		wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;

	jz4740_rtc_wait_ready(rtc_base);

	writel(wakeup_filter_ticks, rtc_base + JZ_REG_RTC_WAKEUP_FILTER);



	/*

	 * Set reset pin low-level assertion time after wakeup: 60 ms.

	 * Range is 0 to 125 ms if RTC is clocked at 32 kHz.

	 */

	reset_counter_ticks = (60 * rtc_rate) / 1000;

	if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)

		reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;

	else

		reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;

	jz4740_rtc_wait_ready(rtc_base);

	writel(reset_counter_ticks, rtc_base + JZ_REG_RTC_RESET_COUNTER);



	jz4740_rtc_wait_ready(rtc_base);

	writel(1, rtc_base + JZ_REG_RTC_HIBERNATE);



	jz4740_halt();

}



void jz4740_reset_init(void)

{

	_machine_restart = jz4740_restart;

	_machine_halt = jz4740_halt;

	pm_power_off = jz4740_power_off;

}