Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d838ff33 authored Dec 23, 2013 by Emilio López

clk: sunxi: add gating support to PLL1



This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>

parent edaf3fb5

Documentation/devicetree/bindings/clock/sunxi.txt

+1 −1

Original line number	Diff line number	Diff line
		@@ -7,7 +7,7 @@ This binding uses the common clock binding[1].
		Required properties:
		- compatible : shall be one of the following:
		"allwinner,sun4i-osc-clk" - for a gatable oscillator
		"allwinner,sun4i-pll1-clk" - for the main PLL clock
		"allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
		"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
		"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
		"allwinner,sun4i-axi-clk" - for the AXI clock

drivers/clk/sunxi/clk-sunxi.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -301,11 +301,13 @@ static struct clk_factors_config sun4i_apb1_config = {
		};

		static const struct factors_data sun4i_pll1_data __initconst = {
		.enable = 31,
		.table = &sun4i_pll1_config,
		.getter = sun4i_get_pll1_factors,
		};

		static const struct factors_data sun6i_a31_pll1_data __initconst = {
		.enable = 31,
		.table = &sun6i_a31_pll1_config,
		.getter = sun6i_a31_get_pll1_factors,
		};