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Commit d8217921 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/powerplay/smu7: drop refresh rate checks for mclk switching 



The logic has moved to cgs.  mclk switching with DC at higher refresh
rates should work.

Reviewed-by: default avatarEric Huang <JinhuiEric.Huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
parent 7a572b1e

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+1 −2
Original line number Original line Diff line number Diff line
@@ -2909,8 +2909,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
	else

	else

		disable_mclk_switching = ((1 < info.display_count) ||

		disable_mclk_switching = ((1 < info.display_count) ||

					  disable_mclk_switching_for_frame_lock ||

					  disable_mclk_switching_for_frame_lock ||

					  smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||

					  smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us));

					  (mode_info.refresh_rate > 120));





	sclk = smu7_ps->performance_levels[0].engine_clock;

	sclk = smu7_ps->performance_levels[0].engine_clock;

	mclk = smu7_ps->performance_levels[0].memory_clock;

	mclk = smu7_ps->performance_levels[0].memory_clock;