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Commit d8026d93 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
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bnx2: Set rx buffer water marks based on MTU. 



The default rx buffer water marks for XOFF/XON are for 1500 MTU.  At
larger MTUs, these water marks need to be adjusted for effective
flow control.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarBenjamin Li <benli@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 5ec6d7bf

drivers/net/bnx2.c

+10 −2
Original line number Diff line number Diff line
@@ -4473,7 +4473,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) 
static int

bnx2_init_chip(struct bnx2 *bp)

{

	u32 val;

	u32 val, mtu;

	int rc, i;



	/* Make sure the interrupt is not active. */
@@ -4565,11 +4565,19 @@ bnx2_init_chip(struct bnx2 *bp) 
	REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);



	/* Program the MTU.  Also include 4 bytes for CRC32. */

	val = bp->dev->mtu + ETH_HLEN + 4;

	mtu = bp->dev->mtu;

	val = mtu + ETH_HLEN + ETH_FCS_LEN;

	if (val > (MAX_ETHERNET_PACKET_SIZE + 4))

		val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;

	REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);



	if (mtu < 1500)

		mtu = 1500;



	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));

	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));

	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));



	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)

		bp->bnx2_napi[i].last_status_idx = 0;

drivers/net/bnx2.h

+21 −0
Original line number Diff line number Diff line
@@ -4199,7 +4199,14 @@ struct l2_fhdr { 


#define BNX2_RBUF_CONFIG				0x0020000c

#define BNX2_RBUF_CONFIG_XOFF_TRIP			 (0x3ffL<<0)

#define BNX2_RBUF_CONFIG_XOFF_TRIP_VAL(mtu)		 \

	((((mtu) - 1500) * 31 / 1000) + 54)

#define BNX2_RBUF_CONFIG_XON_TRIP			 (0x3ffL<<16)

#define BNX2_RBUF_CONFIG_XON_TRIP_VAL(mtu)		 \

	((((mtu) - 1500) * 39 / 1000) + 66)

#define BNX2_RBUF_CONFIG_VAL(mtu)			 \

	(BNX2_RBUF_CONFIG_XOFF_TRIP_VAL(mtu) |		 \

	(BNX2_RBUF_CONFIG_XON_TRIP_VAL(mtu) << 16))



#define BNX2_RBUF_FW_BUF_ALLOC				0x00200010

#define BNX2_RBUF_FW_BUF_ALLOC_VALUE			 (0x1ffL<<7)
@@ -4221,11 +4228,25 @@ struct l2_fhdr { 


#define BNX2_RBUF_CONFIG2				0x0020001c

#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP			 (0x3ffL<<0)

#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL(mtu)	 \

	((((mtu) - 1500) * 4 / 1000) + 5)

#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP			 (0x3ffL<<16)

#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL(mtu)	 \

	((((mtu) - 1500) * 2 / 100) + 30)

#define BNX2_RBUF_CONFIG2_VAL(mtu)			 \

	(BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL(mtu) |	 \

	(BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL(mtu) << 16))



#define BNX2_RBUF_CONFIG3				0x00200020

#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP			 (0x3ffL<<0)

#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL(mtu)		 \

	((((mtu) - 1500) * 12 / 1000) + 18)

#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP			 (0x3ffL<<16)

#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL(mtu)		 \

	((((mtu) - 1500) * 2 / 100) + 30)

#define BNX2_RBUF_CONFIG3_VAL(mtu)			 \

	(BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL(mtu) |	 \

	(BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL(mtu) << 16))



#define BNX2_RBUF_PKT_DATA				0x00208000

#define BNX2_RBUF_CLIST_DATA				0x00210000