Loading drivers/clocksource/arm_arch_timer.c +19 −0 Original line number Diff line number Diff line Loading @@ -52,6 +52,8 @@ #define CNTFRQ 0x10 #define CNTP_TVAL 0x28 #define CNTP_CTL 0x2c #define CNTCVAL_LO 0x30 #define CNTCVAL_HI 0x34 #define CNTV_TVAL 0x38 #define CNTV_CTL 0x3c Loading Loading @@ -902,6 +904,23 @@ bool arch_timer_evtstrm_available(void) return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available); } void arch_timer_mem_get_cval(u32 *lo, u32 *hi) { u32 ctrl; *lo = *hi = ~0U; if (!arch_counter_base) return; ctrl = readl_relaxed_no_log(arch_counter_base + CNTV_CTL); if (ctrl & ARCH_TIMER_CTRL_ENABLE) { *lo = readl_relaxed_no_log(arch_counter_base + CNTCVAL_LO); *hi = readl_relaxed_no_log(arch_counter_base + CNTCVAL_HI); } } static u64 arch_counter_get_cntvct_mem(void) { u32 vct_lo, vct_hi, tmp_hi; Loading include/clocksource/arm_arch_timer.h +5 −0 Original line number Diff line number Diff line Loading @@ -96,6 +96,7 @@ extern u32 arch_timer_get_rate(void); extern u64 (*arch_timer_read_counter)(void); extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void); extern bool arch_timer_evtstrm_available(void); extern void arch_timer_mem_get_cval(u32 *lo, u32 *hi); #else Loading @@ -114,6 +115,10 @@ static inline bool arch_timer_evtstrm_available(void) return false; } static void arch_timer_mem_get_cval(u32 *lo, u32 *hi) { *lo = *hi = ~0U; } #endif #endif Loading
drivers/clocksource/arm_arch_timer.c +19 −0 Original line number Diff line number Diff line Loading @@ -52,6 +52,8 @@ #define CNTFRQ 0x10 #define CNTP_TVAL 0x28 #define CNTP_CTL 0x2c #define CNTCVAL_LO 0x30 #define CNTCVAL_HI 0x34 #define CNTV_TVAL 0x38 #define CNTV_CTL 0x3c Loading Loading @@ -902,6 +904,23 @@ bool arch_timer_evtstrm_available(void) return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available); } void arch_timer_mem_get_cval(u32 *lo, u32 *hi) { u32 ctrl; *lo = *hi = ~0U; if (!arch_counter_base) return; ctrl = readl_relaxed_no_log(arch_counter_base + CNTV_CTL); if (ctrl & ARCH_TIMER_CTRL_ENABLE) { *lo = readl_relaxed_no_log(arch_counter_base + CNTCVAL_LO); *hi = readl_relaxed_no_log(arch_counter_base + CNTCVAL_HI); } } static u64 arch_counter_get_cntvct_mem(void) { u32 vct_lo, vct_hi, tmp_hi; Loading
include/clocksource/arm_arch_timer.h +5 −0 Original line number Diff line number Diff line Loading @@ -96,6 +96,7 @@ extern u32 arch_timer_get_rate(void); extern u64 (*arch_timer_read_counter)(void); extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void); extern bool arch_timer_evtstrm_available(void); extern void arch_timer_mem_get_cval(u32 *lo, u32 *hi); #else Loading @@ -114,6 +115,10 @@ static inline bool arch_timer_evtstrm_available(void) return false; } static void arch_timer_mem_get_cval(u32 *lo, u32 *hi) { *lo = *hi = ~0U; } #endif #endif