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Commit d7ccd8fc authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add drm blit support for evergreen 



This patch implements blit support for bo moves using
the 3D engine.  It uses the same method as r6xx/r7xx:
- store the base state in an IB
- emit variable state and vertex buffers to do the blit

This allows the hw to move bos using the 3D engine and allows
full use of vram beyond the pci aperture size.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 75fa0b08

drivers/gpu/drm/radeon/Makefile

+1 −1
Original line number Original line Diff line number Diff line
@@ -65,7 +65,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \

	rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \

	r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \

	r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \

	r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \

	r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \

	evergreen.o evergreen_cs.o

	evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o





radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

drivers/gpu/drm/radeon/evergreen.c

+29 −22
Original line number Original line Diff line number Diff line
@@ -2062,26 +2062,13 @@ static int evergreen_startup(struct radeon_device *rdev) 
			return r;

			return r;

	}

	}

	evergreen_gpu_init(rdev);

	evergreen_gpu_init(rdev);

#if 0

	if (!rdev->r600_blit.shader_obj) {

		r = r600_blit_init(rdev);

		if (r) {

			DRM_ERROR("radeon: failed blitter (%d).\n", r);

			return r;

		}

	}





	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);

	r = evergreen_blit_init(rdev);

	if (unlikely(r != 0))

		return r;

	r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,

			&rdev->r600_blit.shader_gpu_addr);

	radeon_bo_unreserve(rdev->r600_blit.shader_obj);

	if (r) {

	if (r) {

		DRM_ERROR("failed to pin blit object %d\n", r);

		evergreen_blit_fini(rdev);

		return r;

		rdev->asic->copy = NULL;

		dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);

	}

	}

#endif





	/* allocate wb buffer */

	/* allocate wb buffer */

	r = radeon_wb_init(rdev);

	r = radeon_wb_init(rdev);
@@ -2139,23 +2126,43 @@ int evergreen_resume(struct radeon_device *rdev) 




int evergreen_suspend(struct radeon_device *rdev)

int evergreen_suspend(struct radeon_device *rdev)

{

{

#if 0

	int r;

	int r;

#endif



	/* FIXME: we should wait for ring to be empty */

	/* FIXME: we should wait for ring to be empty */

	r700_cp_stop(rdev);

	r700_cp_stop(rdev);

	rdev->cp.ready = false;

	rdev->cp.ready = false;

	evergreen_irq_suspend(rdev);

	evergreen_irq_suspend(rdev);

	radeon_wb_disable(rdev);

	radeon_wb_disable(rdev);

	evergreen_pcie_gart_disable(rdev);

	evergreen_pcie_gart_disable(rdev);

#if 0



	/* unpin shaders bo */

	/* unpin shaders bo */

	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);

	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);

	if (likely(r == 0)) {

	if (likely(r == 0)) {

		radeon_bo_unpin(rdev->r600_blit.shader_obj);

		radeon_bo_unpin(rdev->r600_blit.shader_obj);

		radeon_bo_unreserve(rdev->r600_blit.shader_obj);

		radeon_bo_unreserve(rdev->r600_blit.shader_obj);

	}

	}

#endif



	return 0;

}



int evergreen_copy_blit(struct radeon_device *rdev,

			uint64_t src_offset, uint64_t dst_offset,

			unsigned num_pages, struct radeon_fence *fence)

{

	int r;



	mutex_lock(&rdev->r600_blit.mutex);

	rdev->r600_blit.vb_ib = NULL;

	r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);

	if (r) {

		if (rdev->r600_blit.vb_ib)

			radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);

		mutex_unlock(&rdev->r600_blit.mutex);

		return r;

	}

	evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);

	evergreen_blit_done_copy(rdev, fence);

	mutex_unlock(&rdev->r600_blit.mutex);

	return 0;

	return 0;

}

}
@@ -2286,7 +2293,7 @@ int evergreen_init(struct radeon_device *rdev) 




void evergreen_fini(struct radeon_device *rdev)

void evergreen_fini(struct radeon_device *rdev)

{

{

	/*r600_blit_fini(rdev);*/

	evergreen_blit_fini(rdev);

	r700_cp_fini(rdev);

	r700_cp_fini(rdev);

	r600_irq_fini(rdev);

	r600_irq_fini(rdev);

	radeon_wb_fini(rdev);

	radeon_wb_fini(rdev);

drivers/gpu/drm/radeon/evergreen_blit_kms.c

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+776 −0

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drivers/gpu/drm/radeon/evergreen_blit_shaders.c

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+359 −0

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drivers/gpu/drm/radeon/evergreen_blit_shaders.h

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+35 −0

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