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Commit d77e70ff authored by Franky Lin's avatar Franky Lin Committed by John W. Linville
Browse files

brcm80211: fmac: add resetcore function for bcm4330 chip



This patch is part of the series of adding new backplane support

Reviewed-by: default avatarArend van Spriel <arend@broadcom.com>
Signed-off-by: default avatarFranky Lin <frankyl@broadcom.com>
Signed-off-by: default avatarArend van Spriel <arend@broadcom.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 086a2e0a
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+2 −3
Original line number Original line Diff line number Diff line
@@ -3108,8 +3108,7 @@ static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)


		ci->coredisable(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
		ci->coredisable(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);


		brcmf_sdio_chip_resetcore(bus->sdiodev, ci,
		ci->resetcore(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM);
					  BCMA_CORE_INTERNAL_MEM);


		/* Clear the top bit of memory */
		/* Clear the top bit of memory */
		if (bus->ramsize) {
		if (bus->ramsize) {
@@ -3133,7 +3132,7 @@ static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
		w_sdreg32(bus, 0xFFFFFFFF,
		w_sdreg32(bus, 0xFFFFFFFF,
			  offsetof(struct sdpcmd_regs, intstatus), &retries);
			  offsetof(struct sdpcmd_regs, intstatus), &retries);


		brcmf_sdio_chip_resetcore(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
		ci->resetcore(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);


		/* Allow HT Clock now that the ARM is running. */
		/* Allow HT Clock now that the ARM is running. */
		bus->alp_only = false;
		bus->alp_only = false;
+41 −4
Original line number Original line Diff line number Diff line
@@ -278,8 +278,8 @@ brcmf_sdio_ai_coredisable(struct brcmf_sdio_dev *sdiodev,
	udelay(1);
	udelay(1);
}
}


void
static void
brcmf_sdio_chip_resetcore(struct brcmf_sdio_dev *sdiodev,
brcmf_sdio_sb_resetcore(struct brcmf_sdio_dev *sdiodev,
			struct chip_info *ci, u16 coreid)
			struct chip_info *ci, u16 coreid)
{
{
	u32 regdata;
	u32 regdata;
@@ -291,7 +291,7 @@ brcmf_sdio_chip_resetcore(struct brcmf_sdio_dev *sdiodev,
	 * Must do the disable sequence first to work for
	 * Must do the disable sequence first to work for
	 * arbitrary current core state.
	 * arbitrary current core state.
	 */
	 */
	ci->coredisable(sdiodev, ci, coreid);
	brcmf_sdio_sb_coredisable(sdiodev, ci, coreid);


	/*
	/*
	 * Now do the initialization sequence.
	 * Now do the initialization sequence.
@@ -301,8 +301,11 @@ brcmf_sdio_chip_resetcore(struct brcmf_sdio_dev *sdiodev,
	brcmf_sdcard_reg_write(sdiodev,
	brcmf_sdcard_reg_write(sdiodev,
			CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4,
			CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4,
			SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET);
			SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET);
	regdata = brcmf_sdcard_reg_read(sdiodev,
				CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
	udelay(1);
	udelay(1);


	/* clear any serror */
	regdata = brcmf_sdcard_reg_read(sdiodev,
	regdata = brcmf_sdcard_reg_read(sdiodev,
				CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), 4);
				CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), 4);
	if (regdata & SSB_TMSHIGH_SERR)
	if (regdata & SSB_TMSHIGH_SERR)
@@ -320,12 +323,44 @@ brcmf_sdio_chip_resetcore(struct brcmf_sdio_dev *sdiodev,
	brcmf_sdcard_reg_write(sdiodev,
	brcmf_sdcard_reg_write(sdiodev,
		CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4,
		CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4,
		SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
		SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
	regdata = brcmf_sdcard_reg_read(sdiodev,
				CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
	udelay(1);
	udelay(1);


	/* leave clock enabled */
	/* leave clock enabled */
	brcmf_sdcard_reg_write(sdiodev,
	brcmf_sdcard_reg_write(sdiodev,
			       CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
			       CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
			       4, SSB_TMSLOW_CLOCK);
			       4, SSB_TMSLOW_CLOCK);
	regdata = brcmf_sdcard_reg_read(sdiodev,
				CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
	udelay(1);
}

static void
brcmf_sdio_ai_resetcore(struct brcmf_sdio_dev *sdiodev,
			struct chip_info *ci, u16 coreid)
{
	u8 idx;
	u32 regdata;

	idx = brcmf_sdio_chip_getinfidx(ci, coreid);

	/* must disable first to work for arbitrary current core state */
	brcmf_sdio_ai_coredisable(sdiodev, ci, coreid);

	/* now do initialization sequence */
	brcmf_sdcard_reg_write(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL,
			       4, BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
	regdata = brcmf_sdcard_reg_read(sdiodev,
					ci->c_inf[idx].wrapbase+BCMA_IOCTL, 4);
	brcmf_sdcard_reg_write(sdiodev, ci->c_inf[idx].wrapbase+BCMA_RESET_CTL,
			       4, 0);
	udelay(1);

	brcmf_sdcard_reg_write(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL,
			       4, BCMA_IOCTL_CLK);
	regdata = brcmf_sdcard_reg_read(sdiodev,
					ci->c_inf[idx].wrapbase+BCMA_IOCTL, 4);
	udelay(1);
	udelay(1);
}
}


@@ -371,11 +406,13 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
		ci->iscoreup = brcmf_sdio_sb_iscoreup;
		ci->iscoreup = brcmf_sdio_sb_iscoreup;
		ci->corerev = brcmf_sdio_sb_corerev;
		ci->corerev = brcmf_sdio_sb_corerev;
		ci->coredisable = brcmf_sdio_sb_coredisable;
		ci->coredisable = brcmf_sdio_sb_coredisable;
		ci->resetcore = brcmf_sdio_sb_resetcore;
		break;
		break;
	case SOCI_AI:
	case SOCI_AI:
		ci->iscoreup = brcmf_sdio_ai_iscoreup;
		ci->iscoreup = brcmf_sdio_ai_iscoreup;
		ci->corerev = brcmf_sdio_ai_corerev;
		ci->corerev = brcmf_sdio_ai_corerev;
		ci->coredisable = brcmf_sdio_ai_coredisable;
		ci->coredisable = brcmf_sdio_ai_coredisable;
		ci->resetcore = brcmf_sdio_ai_resetcore;
		break;
		break;
	default:
	default:
		brcmf_dbg(ERROR, "socitype %u not supported\n", ci->socitype);
		brcmf_dbg(ERROR, "socitype %u not supported\n", ci->socitype);
+2 −2
Original line number Original line Diff line number Diff line
@@ -80,6 +80,8 @@ struct chip_info {
			 u16 coreid);
			 u16 coreid);
	void (*coredisable)(struct brcmf_sdio_dev *sdiodev,
	void (*coredisable)(struct brcmf_sdio_dev *sdiodev,
			struct chip_info *ci, u16 coreid);
			struct chip_info *ci, u16 coreid);
	void (*resetcore)(struct brcmf_sdio_dev *sdiodev,
			struct chip_info *ci, u16 coreid);
};
};


struct sbconfig {
struct sbconfig {
@@ -122,8 +124,6 @@ struct sbconfig {
	u32 sbidhigh;	/* identification */
	u32 sbidhigh;	/* identification */
};
};


extern void brcmf_sdio_chip_resetcore(struct brcmf_sdio_dev *sdiodev,
				      struct chip_info *ci, u16 coreid);
extern int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
extern int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
				  struct chip_info **ci_ptr, u32 regs);
				  struct chip_info **ci_ptr, u32 regs);
extern void brcmf_sdio_chip_detach(struct chip_info **ci_ptr);
extern void brcmf_sdio_chip_detach(struct chip_info **ci_ptr);