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Commit d76fab80 authored Nov 04, 2014 by Dmitry Lavnikevich Committed by Shawn Guo Nov 23, 2014

ARM: dts: pbab01: move i2c pins and frequency configuration into pfla02



Since pins and frequency are specific to module (pfla02), not base board
(pbab02), it is better to be initialized in corresponding dts file.

This patch fixes i2c2, i2c3 pin configuration which caused messages:

imx6q-pinctrl 20e0000.iomuxc: no groups defined in /soc/aips-bus@02000000/iomuxc@020e0000/i2c2grp
imx6q-pinctrl 20e0000.iomuxc: no groups defined in /soc/aips-bus@02000000/iomuxc@020e0000/i2c3grp
imx6q-pinctrl 20e0000.iomuxc: unable to find group for node i2c2grp
imx6q-pinctrl 20e0000.iomuxc: unable to find group for node i2c3grp

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

parent e1bf86ac

arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi

+0 −22

Original line number	Diff line number	Diff line
		@@ -28,9 +28,6 @@
		};

		&i2c2 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c2>;
		clock-frequency = <100000>;
		status = "okay";

		tlv320@18 {
		@@ -55,9 +52,6 @@
		};

		&i2c3 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c3>;
		clock-frequency = <100000>;
		status = "okay";
		};

		@@ -84,19 +78,3 @@
		&usdhc3 {
		status = "okay";
		};

		&iomuxc {
		pinctrl_i2c2: i2c2grp {
		fsl,pins = <
		MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
		MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
		>;
		};

		pinctrl_i2c3: i2c3grp {
		fsl,pins = <
		MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
		MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
		>;
		};
		};

arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi

+26 −0

Original line number	Diff line number	Diff line
		@@ -162,6 +162,18 @@
		};
		};

		&i2c2 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c2>;
		clock-frequency = <100000>;
		};

		&i2c3 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c3>;
		clock-frequency = <100000>;
		};

		&iomuxc {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_hog>;
		@@ -235,6 +247,20 @@
		>;
		};

		pinctrl_i2c2: i2c2grp {
		fsl,pins = <
		MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
		MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
		>;
		};

		pinctrl_i2c3: i2c3grp {
		fsl,pins = <
		MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
		MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
		>;
		};

		pinctrl_uart3: uart3grp {
		fsl,pins = <
		MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1