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Commit d6f0f22c authored by Chris Metcalf's avatar Chris Metcalf
Browse files

arch/tile: update some comments to clarify register usage. 



Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
parent 5592840b

arch/tile/kernel/intvec_32.S

+2 −0
Original line number Diff line number Diff line
@@ -1553,6 +1553,8 @@ STD_ENTRY(_sys_clone) 
 * to be available to it on entry.  It does not modify any callee-save

 * registers (including "lr").  It does not check what PL it is being

 * called at, so you'd better not call it other than at PL0.

 * The <atomic.h> wrapper assumes it only clobbers r20-r29, so if

 * it ever is necessary to use more registers, be aware.

 *

 * It does not use the stack, but since it might be re-interrupted by

 * a page fault which would assume the stack was valid, it does

arch/tile/kernel/process.c

+4 −3
Original line number Diff line number Diff line
@@ -214,9 +214,10 @@ int copy_thread(unsigned long clone_flags, unsigned long sp, 
	/*

	 * Copy the callee-saved registers from the passed pt_regs struct

	 * into the context-switch callee-saved registers area.

	 * We have to restore the callee-saved registers since we may

	 * be cloning a userspace task with userspace register state,

	 * and we won't be unwinding the same kernel frames to restore them.

	 * This way when we start the interrupt-return sequence, the

	 * callee-save registers will be correctly in registers, which

	 * is how we assume the compiler leaves them as we start doing

	 * the normal return-from-interrupt path after calling C code.

	 * Zero out the C ABI save area to mark the top of the stack.

	 */

	ksp = (unsigned long) childregs;