Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d6c69803 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Clear display interrupt before enabling when turning on the power well 



For a bit of extra paranoia make sure the display irqs are all cleared
before we enabled them when turning on the power well. This should
really be the case already since the power well was off which resets
everything.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460382992-28728-6-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
parent 8bb61306

drivers/gpu/drm/i915/i915_irq.c

+3 −8
Original line number Diff line number Diff line
@@ -3309,13 +3309,6 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) 
	u32 iir_mask;

	enum pipe pipe;



	pipestat_mask = PIPESTAT_INT_STATUS_MASK |

			PIPE_FIFO_UNDERRUN_STATUS;



	for_each_pipe(dev_priv, pipe)

		I915_WRITE(PIPESTAT(pipe), pipestat_mask);

	POSTING_READ(PIPESTAT(PIPE_A));



	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |

			PIPE_CRC_DONE_INTERRUPT_STATUS;
@@ -3699,9 +3692,11 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) 


	dev_priv->display_irqs_enabled = true;



	if (intel_irqs_enabled(dev_priv))

	if (intel_irqs_enabled(dev_priv)) {

		vlv_display_irq_reset(dev_priv);

		vlv_display_irq_postinstall(dev_priv);

	}

}



void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)

{