Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d6ba745d authored by Prabhakar Kushwaha's avatar Prabhakar Kushwaha Committed by Artem Bityutskiy
Browse files

mtd: fsl_ifc_nand: wait tWB time, poll R/B before command execution 



IFC_FIR_OP_CMD0 issues command for execution without checking flash
readiness. It may cause problem if flash is not ready. Instead use
IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or
time-out, before issuing command.

NAND_CMD_READID command implemention does not fulfill above requirement. So
update its programming.

Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: default avatarHemant Nautiyal <hemant.nautiyal@freescale.com>
Signed-off-by: default avatarArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
parent 5d27aa5a

drivers/mtd/nand/fsl_ifc_nand.c

+2 −2
Original line number Diff line number Diff line
@@ -389,7 +389,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, 
			timing = IFC_FIR_OP_RBCD;



		out_be32(&ifc->ifc_nand.nand_fir0,

				(IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |

				(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |

				(IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |

				(timing << IFC_NAND_FIR0_OP2_SHIFT));

		out_be32(&ifc->ifc_nand.nand_fcr0,
@@ -754,7 +754,7 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv) 


	/* READID */

	out_be32(&ifc->ifc_nand.nand_fir0,

			(IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |

			(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |

			(IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |

			(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));

	out_be32(&ifc->ifc_nand.nand_fcr0,