Commit d68827c6 authored Jul 19, 2016 by Stefan Agner Committed by Greg Kroah-Hartman Aug 31, 2016

tty: serial: fsl_lpuart: fix clearing of receive flag

Commit 8e4934c6 ("tty: serial: fsl_lpuart: clear receive flag on FIFO
flush") implemented clearing of the receive flag by reading the status register
only. It turned out that even though we flush the FIFO afterwards, a explicit
read of the data register is still required.

This leads to a FIFO underrun. To avoid this, follow the advice in the overrun
"Operation section": Unconditionally clear RXUF after using RXFLUSH.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent d6b0d2f2

drivers/tty/serial/fsl_lpuart.c

+6 −3

Original line number	Diff line number	Diff line
		@@ -935,13 +935,16 @@ static void lpuart_setup_watermark(struct lpuart_port *sport)
		writeb(val \| UARTPFIFO_TXFE \| UARTPFIFO_RXFE,
		sport->port.membase + UARTPFIFO);

		/* explicitly clear RDRF */
		readb(sport->port.membase + UARTSR1);

		/* flush Tx and Rx FIFO */
		writeb(UARTCFIFO_TXFLUSH \| UARTCFIFO_RXFLUSH,
		sport->port.membase + UARTCFIFO);

		/* explicitly clear RDRF */
		if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
		readb(sport->port.membase + UARTDR);
		writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
		}

		writeb(0, sport->port.membase + UARTTWFIFO);
		writeb(1, sport->port.membase + UARTRWFIFO);