Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d65a634a authored by Zi Shen Lim's avatar Zi Shen Lim Committed by Catalin Marinas
Browse files

arm64: bpf: add 'shift by register' instructions 



Commit 72b603ee ("bpf: x86: add missing 'shift by register'
instructions to x64 eBPF JIT") noted support for 'shift by register'
in eBPF and added support for it for x64. Let's enable this for arm64
as well.

The arm64 eBPF JIT compiler now passes the new 'shift by register'
test case introduced in the same commit 72b603ee.

Signed-off-by: default avatarZi Shen Lim <zlim.lnx@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent b569c1c6

arch/arm64/net/bpf_jit.h

+6 −2
Original line number Diff line number Diff line
@@ -144,8 +144,12 @@ 


/* Data-processing (2 source) */

/* Rd = Rn OP Rm */

#define A64_UDIV(sf, Rd, Rn, Rm) aarch64_insn_gen_data2(Rd, Rn, Rm, \

	A64_VARIANT(sf), AARCH64_INSN_DATA2_UDIV)

#define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \

	A64_VARIANT(sf), AARCH64_INSN_DATA2_##type)

#define A64_UDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, UDIV)

#define A64_LSLV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSLV)

#define A64_LSRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSRV)

#define A64_ASRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, ASRV)



/* Data-processing (3 source) */

/* Rd = Ra + Rn * Rm */

arch/arm64/net/bpf_jit_comp.c

+12 −0
Original line number Diff line number Diff line
@@ -261,6 +261,18 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx) 
		emit(A64_MUL(is64, tmp, tmp, src), ctx);

		emit(A64_SUB(is64, dst, dst, tmp), ctx);

		break;

	case BPF_ALU | BPF_LSH | BPF_X:

	case BPF_ALU64 | BPF_LSH | BPF_X:

		emit(A64_LSLV(is64, dst, dst, src), ctx);

		break;

	case BPF_ALU | BPF_RSH | BPF_X:

	case BPF_ALU64 | BPF_RSH | BPF_X:

		emit(A64_LSRV(is64, dst, dst, src), ctx);

		break;

	case BPF_ALU | BPF_ARSH | BPF_X:

	case BPF_ALU64 | BPF_ARSH | BPF_X:

		emit(A64_ASRV(is64, dst, dst, src), ctx);

		break;

	/* dst = -dst */

	case BPF_ALU | BPF_NEG:

	case BPF_ALU64 | BPF_NEG: