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Commit d629336b authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Don't set the fence number in DPFC_CTL on SNB 



SNB has another register where the actual FBC CPU fence number is
stored. The documenation explicitly states that the fence number
in DPFC_CTL must be 0 on SNB. And in fact when it's not zero,
the GTT tracking simply doesn't work.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b33ecdd1

drivers/gpu/drm/i915/intel_pm.c

+3 −1
Original line number Diff line number Diff line
@@ -222,7 +222,9 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
	dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);

	/* Set persistent mode for front-buffer rendering, ala X. */

	dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;

	dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);

	dpfc_ctl |= DPFC_CTL_FENCE_EN;

	if (IS_GEN5(dev))

		dpfc_ctl |= obj->fence_reg;

	I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);



	I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |