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Unverified Commit d628d952 authored by Michael Bestas's avatar Michael Bestas
Browse files

Merge tag 'MMI-S2SN32.34-60' into android13-4.19-kona 

* tag 'MMI-S2SN32.34-60':
  ARM: dts: msm: Add support for tioman gpio for Khaje
  ARM: dts: msm: Add flash support for khaje
  ARM: dts: msm: Add sensor devicetree for khaje camera
  ARM: dts: msm: Add CSIPHY/CCI nodes for khaje
  ARM: dts: msm: Add camera device tree support for Khaje Camera
  ARM: dts: msm: Add tpg node to bengal device tree
  ARM: dts: msm: fix wrong IRQ type for TFE
  ARM: dts: msm: Fix the svs voting level for scuba csiphy
  ARM: dts: msm: camera: disable gpu mitigation
  ARM: dts: msm: camera: ope: Change turbo clock corner
  ARM: dts: msm: camera: Add tfe2 fuse info to cpas node
  ARM: dts: msm: Add GMSL camera DTSI for robotics RB5
  ARM: dts: msm: camera: ope: enabled debugfs support for clk level
  ARM: dts: msm: Fix the vdig voltage for front camera
  ARM: dts: msm: Add support for robotics RB5 camera
  ARM: dts: msm: Remove fuse setting for secure camera
  ARM: dts: msm: camera: Add support to Cx Ipeak
  ARM: dts: msm: Update PHY version for bengal target
  ARM: dts: msm: camera: cpas: Disable secure feature mask
  ARM: dts: msm: Fix compilation issue for scuba-camera-sensor-idp
  ARM: dts: msm: Update GPU Mitigation
  ARM: dts: msm: Add Camera Sensor nodes for IDP/IDPS for scuba
  ARM: dts: msm: Fix the phy regulator voltage
  ARM: dts: msm: Add cci and csiphy support for Scuba camera
  ARM: dts: msm: Fix Bus and TFE nodes in Scuba camera
  ARM: dts: msm: Add support for Scuba camera
  ARM: dts: msm: Add csiphy3 and cci1 clients to cpas
  ARM: dts: msm: Change CSID and VFE interrupt name for lagoon camera
  ARM: dts: msm: Change IPE Write port, IPE clock source for lagoon camera
  ARM: dts: msm: Add csiphy and cci nodes in lagoon camera DT
  ARM: dts: msm: Update clock header for lagoon
  ARM: dts: msm: Add camera sensor nodes in MTP/CDP for lagoon
  ARM: dts: msm: camera: ope: Change BL fifo depth
  ARM: dts: msm: Add support for Kona XR platform camera hardware
  ARM: dts: msm: Change the vdig voltage of bengal front camera
  ARM: dts: msm: Change the vdig voltage of bengal front camera
  ARM: dts: msm: Fix order of clock naming in csid lite node for kona
  ARM: dts: msm: camera: Update fifo depth for OPE CDM
  ARM: dts: msm: Add CAMNOC nodes in lagoon camera dtsi
  ARM: dts: msm: Override csiphy version for lito v2
  ARM: dts: msm: camera: cpas: Add GPU Limit support
  ARM: dts: msm: Add lagoon camera dtsi
  dt-bindings: camera: Add CSID and IFE support for lagoon
  ARM: dts: msm: Fix inverted image on front camera
  ARM: dts: msm: camera: Correct the clock rates for all modules
  ARM: dts: msm: Add support to discard a region in dma space
  ARM: dts: msm: Fix orientation of front camera
  ARM: dts: msm: Add camera dts nodes for Bengal QRD
  ARM: dts: msm: camera: Add support to Cx Ipeak
  ARM: dts: msm: camera: smmu: Fix camera SID issue
  ARM: dts: msm: camera: cpas: Add camera fuse support
  ARM: dts: msm: camera: cci: Add cci version
  ARM: dts: msm: Fix orientation of camera sensors
  ARM: dts: msm: Fix the reset gpio for rear aux camera
  ARM: dts: msm: camera: cpas: Add constituent paths for OPE
  ARM: dts: msm: camera: Add required clocks to tpg and cpas node
  ARM: dts: msm: Fix svs clock level for bengal
  ARM: dts: msm: Fix custom gpio tables for bengal
  ARM: dts: msm: Add support for camera hardware for bengal platform
  ARM: dts: msm: Add dtsi nodes for csiphy and cci
  dt-bindings: camera: Add CDM support
  dt-bindings: camera: Add TFE support
  ARM: dts: msm: Add support for target SM4250

 Conflicts:
	arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera-sensor-idp.dtsi
	arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera-sensor-qrd.dtsi
	arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera.dtsi
	arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-csiphy.txt
	arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-rb5.dtsi
	arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xr.dtsi
	arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera-sensor-cdp.dtsi
	arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera-sensor-mtp.dtsi
	arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera.dtsi
	arch/arm64/boot/dts/vendor/qcom/camera/scuba-camera-sensor-idp.dtsi
	arch/arm64/boot/dts/vendor/qcom/camera/scuba-camera.dtsi

Change-Id: Ief1f21727ae2c9c5c280e5d8976b6eb6825ca8c3
parents 491a7791 50be3420

arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera-sensor-idp.dtsi

+92 −15
Original line number Diff line number Diff line
@@ -118,8 +118,8 @@ 
				&cam_sensor_rear1_reset_active>;

		pinctrl-1 = <&cam_sensor_mclk1_suspend

				&cam_sensor_rear1_reset_suspend>;

		gpios = <&tlmm 19 0>,

			<&tlmm 21 0>;

		gpios = <&tlmm 21 0>,

			<&tlmm 19 0>;

		gpio-reset = <1>;

		gpio-req-tbl-num = <0 1>;

		gpio-req-tbl-flags = <1 0>;
@@ -145,8 +145,8 @@ 
			"cam_clk";

		rgltr-cntrl-support;

		pwm-switch;

		rgltr-min-voltage = <1800000 2800000 1056000 0>;

		rgltr-max-voltage = <1800000 2800000 1056000 0>;

		rgltr-min-voltage = <1800000 2800000 1050000 0>;

		rgltr-max-voltage = <1800000 2800000 1050000 0>;

		rgltr-load-current = <0 80000 105000 0>;

		gpio-no-mux = <0>;

		pinctrl-names = "cam_default", "cam_suspend";
@@ -211,7 +211,7 @@ 
		cell-index = <0>;

		compatible = "qcom,cam-sensor";

		csiphy-sd-index = <0>;

		sensor-position-roll = <90>;

		sensor-position-roll = <270>;

		sensor-position-pitch = <0>;

		sensor-position-yaw = <180>;

		actuator-src = <&actuator_rear>;
@@ -255,7 +255,7 @@ 
		cell-index = <1>;

		compatible = "qcom,cam-sensor";

		csiphy-sd-index = <1>;

		sensor-position-roll = <90>;

		sensor-position-roll = <270>;

		sensor-position-pitch = <0>;

		sensor-position-yaw = <180>;

		actuator-src = <&actuator_rear_aux>;
@@ -278,8 +278,8 @@ 
				&cam_sensor_rear1_reset_active>;

		pinctrl-1 = <&cam_sensor_mclk1_suspend

				&cam_sensor_rear1_reset_suspend>;

		gpios = <&tlmm 19 0>,

			<&tlmm 21 0>;

		gpios = <&tlmm 21 0>,

			<&tlmm 19 0>;

		gpio-reset = <1>;

		gpio-req-tbl-num = <0 1>;

		gpio-req-tbl-flags = <1 0>;
@@ -299,9 +299,9 @@ 
		cell-index = <2>;

		compatible = "qcom,cam-sensor";

		csiphy-sd-index = <2>;

		sensor-position-roll = <90>;

		sensor-position-roll = <270>;

		sensor-position-pitch = <0>;

		sensor-position-yaw = <180>;

		sensor-position-yaw = <0>;

		eeprom-src = <&eeprom_front>;

		cam_vio-supply = <&L7P>;

		cam_vana-supply = <&L6P>;
@@ -311,8 +311,8 @@ 
			"cam_clk";

		rgltr-cntrl-support;

		pwm-switch;

		rgltr-min-voltage = <1800000 2800000 1056000 0>;

		rgltr-max-voltage = <1800000 2800000 1056000 0>;

		rgltr-min-voltage = <1800000 2800000 1050000 0>;

		rgltr-max-voltage = <1800000 2800000 1050000 0>;

		rgltr-load-current = <0 80000 105000 0>;

		gpio-no-mux = <0>;

		pinctrl-names = "cam_default", "cam_suspend";
@@ -329,10 +329,14 @@ 
			<&tlmm 66 0>,

			<&tlmm 67 0>;

		gpio-reset = <1>;

		gpio-custom1 = <2>;

		gpio-custom2 = <3>;

		gpio-req-tbl-num = <0 1>;

		gpio-req-tbl-flags = <1 0>;

		gpio-req-tbl-label = "CAMIF_MCLK2",

					"CAM_RESET2";

					"CAM_RESET2",

					"CAM_CSIMUX_OE0",

					"CAM_CSIMUX_SEL0";

		sensor-mode = <0>;

		cci-master = <1>;

		status = "ok";
@@ -347,7 +351,7 @@ 
		cell-index = <3>;

		compatible = "qcom,cam-sensor";

		csiphy-sd-index = <2>;

		sensor-position-roll = <90>;

		sensor-position-roll = <270>;

		sensor-position-pitch = <0>;

		sensor-position-yaw = <180>;

		led-flash-src = <&led_flash_rear_aux2>;
@@ -378,10 +382,14 @@ 
			<&tlmm 66 0>,

			<&tlmm 67 0>;

		gpio-reset = <1>;

		gpio-custom1 = <2>;

		gpio-custom2 = <3>;

		gpio-req-tbl-num = <0 1>;

		gpio-req-tbl-flags = <1 0>;

		gpio-req-tbl-label = "CAMIF_MCLK3",

					"CAM_RESET3";

					"CAM_RESET3",

					"CAM_CSIMUX_OE1",

					"CAM_CSIMUX_SEL1";

		sensor-mode = <0>;

		cci-master = <0>;

		status = "ok";
@@ -390,4 +398,73 @@ 
		clock-cntl-level = "turbo";

		clock-rates = <19200000>;

	};



	/*TPG0*/

	qcom,cam-tpg0 {

		cell-index = <4>;

		compatible = "qcom,cam-sensor";

		csiphy-sd-index = <4>;

		sensor-position-roll = <270>;

		sensor-position-pitch = <0>;

		sensor-position-yaw = <180>;

		gpios = <&tlmm 30 0>,

			<&tlmm 35 0>;

		gpio-reset = <1>;

		gpio-req-tbl-num = <0 1>;

		gpio-req-tbl-flags = <1 0>;

		gpio-req-tbl-label = "CAMIF_MCLK1",

					"CAM_RESET1";

		sensor-mode = <0>;

		status = "ok";

		clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;

		clock-names = "cam_clk";

		clock-cntl-level = "turbo";

		clock-rates = <19200000>;

	};



	/*TPG1*/

	qcom,cam-tpg1 {

		cell-index = <5>;

		compatible = "qcom,cam-sensor";

		csiphy-sd-index = <5>;

		sensor-position-roll = <270>;

		sensor-position-pitch = <0>;

		sensor-position-yaw = <180>;

		gpios = <&tlmm 30 0>,

			<&tlmm 35 0>;

		gpio-reset = <1>;

		gpio-req-tbl-num = <0 1>;

		gpio-req-tbl-flags = <1 0>;

		gpio-req-tbl-label = "CAMIF_MCLK1",

					"CAM_RESET1";

		sensor-mode = <0>;

		status = "ok";

		clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;

		clock-names = "cam_clk";

		clock-cntl-level = "turbo";

		clock-rates = <19200000>;

	};



	/*TPG2*/

	qcom,cam-tpg2 {

		cell-index = <6>;

		compatible = "qcom,cam-sensor";

		csiphy-sd-index = <6>;

		sensor-position-roll = <270>;

		sensor-position-pitch = <0>;

		sensor-position-yaw = <180>;

		gpios = <&tlmm 30 0>,

			<&tlmm 35 0>;

		gpio-reset = <1>;

		gpio-req-tbl-num = <0 1>;

		gpio-req-tbl-flags = <1 0>;

		gpio-req-tbl-label = "CAMIF_MCLK1",

					"CAM_RESET1";

		sensor-mode = <0>;

		status = "ok";

		clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;

		clock-names = "cam_clk";

		clock-cntl-level = "turbo";

		clock-rates = <19200000>;

	};

};

arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera-sensor-qrd.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -145,8 +145,8 @@ 
			"cam_clk";

		rgltr-cntrl-support;

		pwm-switch;

		rgltr-min-voltage = <1800000 2800000 1056000 0>;

		rgltr-max-voltage = <1800000 2800000 1056000 0>;

		rgltr-min-voltage = <1800000 2800000 1050000 0>;

		rgltr-max-voltage = <1800000 2800000 1050000 0>;

		rgltr-load-current = <0 80000 105000 0>;

		gpio-no-mux = <0>;

		pinctrl-names = "cam_default", "cam_suspend";
@@ -301,7 +301,7 @@ 
		cell-index = <2>;

		compatible = "qcom,cam-sensor";

		csiphy-sd-index = <2>;

		sensor-position-roll = <90>;

		sensor-position-roll = <270>;

		sensor-position-pitch = <0>;

		sensor-position-yaw = <0>;

		eeprom-src = <&eeprom_front>;
@@ -313,8 +313,8 @@ 
			"cam_clk";

		rgltr-cntrl-support;

		pwm-switch;

		rgltr-min-voltage = <1800000 2800000 1056000 0>;

		rgltr-max-voltage = <1800000 2800000 1056000 0>;

		rgltr-min-voltage = <1800000 2800000 1050000 0>;

		rgltr-max-voltage = <1800000 2800000 1050000 0>;

		rgltr-load-current = <0 80000 105000 0>;

		gpio-no-mux = <0>;

		pinctrl-names = "cam_default", "cam_suspend";

arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera.dtsi

+98 −86
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 


	cam_csiphy0: qcom,csiphy0 {

		cell-index = <0>;

		compatible = "qcom,csiphy-v2.0", "qcom,csiphy";

		compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy";

		reg = <0x05C52000 0x1000>;

		reg-names = "csiphy";

		reg-cam-base = <0x52000>;
@@ -30,15 +30,16 @@ 
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";

		clock-rates =

			<19200000  0 19200000 0>,

			<341330000 0 200000000 0>,

			<240000000 0 200000000 0>,

			<341330000 0 200000000 0>,

			<384000000 0 268800000 0>;

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;

		status = "ok";

	};



	cam_csiphy1: qcom,csiphy1 {

		cell-index = <1>;

		compatible = "qcom,csiphy-v2.0", "qcom,csiphy";

		compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy";

		reg = <0x05C53000 0x1000>;

		reg-names = "csiphy";

		reg-cam-base = <0x53000>;
@@ -60,15 +61,16 @@ 
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";

		clock-rates =

			<19200000  0 19200000 0>,

			<341330000 0 200000000 0>,

			<240000000 0 200000000 0>,

			<341330000 0 200000000 0>,

			<384000000 0 268800000 0>;

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;

		status = "ok";

	};



	cam_csiphy2: qcom,csiphy2 {

		cell-index = <2>;

		compatible = "qcom,csiphy-v2.0", "qcom,csiphy";

		compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy";

		reg = <0x05C54000 0x1000>;

		reg-names = "csiphy";

		reg-cam-base = <0x54000>;
@@ -90,15 +92,16 @@ 
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";

		clock-rates =

			<19200000  0 19200000 0>,

			<341330000 0 200000000 0>,

			<240000000 0 200000000 0>,

			<341330000 0 200000000 0>,

			<384000000 0 268800000 0>;

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;

		status = "ok";

	};



	cam_cci0: qcom,cci0 {

		cell-index = <0>;

		compatible = "qcom,cci";

		compatible = "qcom,cci-v1.2", "qcom,cci";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x05C1B000 0x1000>;
@@ -197,8 +200,7 @@ 


		msm_cam_smmu_tfe {

			compatible = "qcom,msm-cam-smmu-cb";

			iommus = <&apps_smmu 0x400 0x000>,

				<&apps_smmu 0x401 0x000>;

			iommus = <&apps_smmu 0x400 0x000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;

			label = "tfe";
@@ -217,9 +219,7 @@ 
		msm_cam_smmu_ope {

			compatible = "qcom,msm-cam-smmu-cb";

			iommus = <&apps_smmu 0x820 0x000>,

				<&apps_smmu 0x821 0x020>,

				<&apps_smmu 0x840 0x000>,

				<&apps_smmu 0x841 0x000>;

				<&apps_smmu 0x840 0x000>;

			qcom,iommu-faults = "non-fatal";

			multiple-client-devices;

			qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
@@ -238,8 +238,7 @@ 


		msm_cam_smmu_cpas_cdm {

			compatible = "qcom,msm-cam-smmu-cb";

			iommus = <&apps_smmu 0x800 0x000>,

				<&apps_smmu 0x801 0x020>;

			iommus = <&apps_smmu 0x800 0x000>;

			label = "cpas-cdm0";

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
@@ -273,6 +272,8 @@ 
		reg = <0x5c11000 0x1000>,

			<0x5c13000 0x4000>;

		reg-cam-base = <0x11000 0x13000>;

		cam_hw_fuse = <CAM_CPAS_ISP_FUSE_ID   0x01B401D0 5 CAM_CPAS_FEATURE_TYPE_DISABLE  2>,

			<CAM_CPAS_ISP_PIX_FUSE_ID 0x01B401D0 6 CAM_CPAS_FEATURE_TYPE_DISABLE  2>;

		interrupt-names = "cpas_camnoc";

		interrupts = <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>;

		camnoc-axi-min-ib-bw = <3000000000>;  /*Need to be verified*/
@@ -283,37 +284,42 @@ 
			"gcc_camss_top_ahb_clk",

			"gcc_camss_top_ahb_clk_src",

			"gcc_camss_axi_clk",

			"gcc_camss_axi_clk_src";

			"gcc_camss_axi_clk_src",

			"gcc_camss_nrt_axi_clk",

			"gcc_camss_rt_axi_clk";

		clocks =

			<&gcc GCC_CAMERA_AHB_CLK>,

			<&gcc GCC_CAMSS_TOP_AHB_CLK>,

			<&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>,

			<&gcc GCC_CAMSS_AXI_CLK>,

			<&gcc GCC_CAMSS_AXI_CLK_SRC>;

			<&gcc GCC_CAMSS_AXI_CLK_SRC>,

			<&gcc GCC_CAMSS_NRT_AXI_CLK>,

			<&gcc GCC_CAMSS_RT_AXI_CLK>;

		src-clock-name = "gcc_camss_axi_clk_src";

		clock-rates =

			<0        0        0         0         0>,

			<0 80000000 80000000  19200000  19200000>,

			<0 80000000 80000000 150000000 150000000>,

			<0 80000000 80000000 200000000 200000000>,

			<0 80000000 80000000 300000000 300000000>,

			<0 80000000 80000000 300000000 300000000>,

			<0 80000000 80000000 300000000 300000000>;

			<0 0        0 0         0 0 0>,

			<0 0 80000000 0  19200000 0 0>,

			<0 0 80000000 0 150000000 0 0>,

			<0 0 80000000 0 200000000 0 0>,

			<0 0 80000000 0 300000000 0 0>,

			<0 0 80000000 0 300000000 0 0>,

			<0 0 80000000 0 300000000 0 0>;

		clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs",

			"svs_l1", "nominal", "turbo";

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;

		control-camnoc-axi-clk;

		camnoc-bus-width = <32>;

		camnoc-axi-clk-bw-margin-perc = <20>;

		qcom,msm-bus,name = "cam_ahb"; /*Need to verify*/

		qcom,msm-bus,num-cases = <7>; /*Need to verify*/

		qcom,msm-bus,num-paths = <1>; /*Need to verify*/

		qcom,msm-bus,vectors-KBps = /*Need to verify*/

		qcom,msm-bus,name = "cam_ahb";

		qcom,msm-bus,num-cases = <7>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<MSM_BUS_MASTER_AMPSS_M0

			MSM_BUS_SLAVE_CAMERA_CFG 0 0>,

			<MSM_BUS_MASTER_AMPSS_M0

			MSM_BUS_SLAVE_CAMERA_CFG 0 76800>,

			MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,

			<MSM_BUS_MASTER_AMPSS_M0

			MSM_BUS_SLAVE_CAMERA_CFG 0 76800>,

			MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,

			<MSM_BUS_MASTER_AMPSS_M0

			MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,

			<MSM_BUS_MASTER_AMPSS_M0
@@ -417,6 +423,10 @@ 
					traffic-data = <CAM_CPAS_PATH_DATA_ALL>;

					traffic-transaction-type =

					<CAM_CPAS_TRANSACTION_WRITE>;

					constituent-paths =

						<CAM_CPAS_PATH_DATA_OPE_WR_VID

						CAM_CPAS_PATH_DATA_OPE_WR_DISP

						CAM_CPAS_PATH_DATA_OPE_WR_REF>;

					parent-node = <&level1_nrt0_rd_wr>;

				};
@@ -427,6 +437,9 @@ 
					traffic-data = <CAM_CPAS_PATH_DATA_ALL>;

					traffic-transaction-type =

					<CAM_CPAS_TRANSACTION_READ>;

					constituent-paths =

						<CAM_CPAS_PATH_DATA_OPE_RD_IN

						CAM_CPAS_PATH_DATA_OPE_RD_REF>;

					parent-node = <&level1_nrt0_rd_wr>;

				};
@@ -591,23 +604,22 @@ 
			"cphy_rx_clk_src",

			"tfe_cphy_rx_clk",

			"tfe_clk_src",

			"tfe_clk",

			"tfe_axi_clk";

			"tfe_clk";

		clocks =

			<&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_0_CSID_CLK>,

			<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,

			<&gcc GCC_CAMSS_TFE_0_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_0_CLK>,

			<&gcc GCC_CAMSS_AXI_CLK>;

			<&gcc GCC_CAMSS_TFE_0_CLK>;

		clock-rates =

			<240000000 240000000 0 240000000 256000000 256000000 150000000>,

			<384000000 384000000 0 341333333 460800000 460800000 200000000>,

			<426400000 426400000 0 384000000 576000000 576000000 300000000>;

			<240000000 0 240000000 0 256000000 0>,

			<384000000 0 341333333 0 460800000 0>,

			<426400000 0 384000000 0 576000000 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "tfe_csid_clk_src";

		clock-control-debugfs = "true";

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;

		status = "ok";

	};
@@ -623,19 +635,18 @@ 
		camss-supply = <&gcc_camss_top_gdsc>;

		clock-names =

			"tfe_clk_src",

			"tfe_clk",

			"tfe_axi_clk";

			"tfe_clk";

		clocks =

			<&gcc GCC_CAMSS_TFE_0_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_0_CLK>,

			<&gcc GCC_CAMSS_AXI_CLK>;

			<&gcc GCC_CAMSS_TFE_0_CLK>;

		clock-rates =

			<256000000 256000000 150000000>,

			<460800000 460800000 200000000>,

			<576000000 576000000 300000000>;

			<256000000 0>,

			<460800000 0>,

			<576000000 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "tfe_clk_src";

		clock-control-debugfs = "true";

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;

		status = "ok";

	};
@@ -657,23 +668,22 @@ 
			"cphy_rx_clk_src",

			"tfe_cphy_rx_clk",

			"tfe_clk_src",

			"tfe_clk",

			"tfe_axi_clk";

			"tfe_clk";

		clocks =

			<&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_1_CSID_CLK>,

			<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,

			<&gcc GCC_CAMSS_TFE_1_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_1_CLK>,

			<&gcc GCC_CAMSS_AXI_CLK>;

			<&gcc GCC_CAMSS_TFE_1_CLK>;

		clock-rates =

			<240000000 240000000 0 240000000 256000000 256000000 150000000>,

			<384000000 384000000 0 341333333 460800000 460800000 200000000>,

			<426400000 426400000 0 384000000 576000000 576000000 300000000>;

			<240000000 0 240000000 0 256000000 0>,

			<384000000 0 341333333 0 460800000 0>,

			<426400000 0 384000000 0 576000000 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "tfe_csid_clk_src";

		clock-control-debugfs = "true";

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;

		status = "ok";

	};
@@ -684,24 +694,23 @@ 
		reg = <0x5c75000 0x5000>;

		reg-cam-base = <0x75000>;

		interrupt-names = "tfe1";

		interrupts = <0 213 0>;

		interrupts = <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;

		regulator-names = "camss";

		camss-supply = <&gcc_camss_top_gdsc>;

		clock-names =

			"tfe_clk_src",

			"tfe_clk",

			"tfe_axi_clk";

			"tfe_clk";

		clocks =

			<&gcc GCC_CAMSS_TFE_1_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_1_CLK>,

			<&gcc GCC_CAMSS_AXI_CLK>;

			<&gcc GCC_CAMSS_TFE_1_CLK>;

		clock-rates =

			<256000000 256000000 150000000>,

			<460800000 460800000 200000000>,

			<576000000 576000000 300000000>;

			<256000000 0>,

			<460800000 0>,

			<576000000 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "tfe_clk_src";

		clock-control-debugfs = "true";

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;

		status = "ok";

	};
@@ -723,23 +732,22 @@ 
			"cphy_rx_clk_src",

			"tfe_cphy_rx_clk",

			"tfe_clk_src",

			"tfe_clk",

			"tfe_axi_clk";

			"tfe_clk";

		clocks =

			<&gcc GCC_CAMSS_TFE_2_CSID_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_2_CSID_CLK>,

			<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_2_CPHY_RX_CLK>,

			<&gcc GCC_CAMSS_TFE_2_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_2_CLK>,

			<&gcc GCC_CAMSS_AXI_CLK>;

			<&gcc GCC_CAMSS_TFE_2_CLK>;

		clock-rates =

			<240000000 240000000 0 240000000 256000000 256000000 150000000>,

			<384000000 384000000 0 341333333 460800000 460800000 200000000>,

			<426400000 426400000 0 384000000 576000000 576000000 300000000>;

			<240000000 0 240000000 0 256000000 0>,

			<384000000 0 341333333 0 460800000 0>,

			<426400000 0 384000000 0 576000000 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "tfe_csid_clk_src";

		clock-control-debugfs = "true";

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;

		status = "ok";

	};
@@ -755,19 +763,18 @@ 
		camss-supply = <&gcc_camss_top_gdsc>;

		clock-names =

			"tfe_clk_src",

			"tfe_clk",

			"tfe_axi_clk";

			"tfe_clk";

		clocks =

			<&gcc GCC_CAMSS_TFE_2_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_2_CLK>,

			<&gcc GCC_CAMSS_AXI_CLK>;

			<&gcc GCC_CAMSS_TFE_2_CLK>;

		clock-rates =

			<256000000 256000000 150000000>,

			<460800000 460800000 200000000>,

			<576000000 576000000 300000000>;

			<256000000 0>,

			<460800000 0>,

			<576000000 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "tfe_clk_src";

		clock-control-debugfs = "true";

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;

		status = "ok";

	};
@@ -782,14 +789,16 @@ 
		camss-supply = <&gcc_camss_top_gdsc>;

		clock-names =

			"cphy_rx_clk_src",

			"tfe_0_cphy_rx_clk";

			"tfe_0_cphy_rx_clk",

			"gcc_camss_cphy_0_clk";

		clocks =

			<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>;

			<&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,

			<&gcc GCC_CAMSS_CPHY_0_CLK>;

		clock-rates =

			<240000000 240000000>,

			<341333333 341333333>,

			<384000000 384000000>;

			<240000000 0 0>,

			<341333333 0 0>,

			<384000000 0 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "cphy_rx_clk_src";

		clock-control-debugfs = "false";
@@ -807,14 +816,16 @@ 
		camss-supply = <&gcc_camss_top_gdsc>;

		clock-names =

			"cphy_rx_clk_src",

			"tfe_1_cphy_rx_clk";

			"tfe_1_cphy_rx_clk",

			"gcc_camss_cphy_1_clk";

		clocks =

			<&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>;

			<&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,

			<&gcc GCC_CAMSS_CPHY_1_CLK>;

		clock-rates =

			<240000000 240000000>,

			<341333333 341333333>,

			<384000000 384000000>;

			<240000000 0 0>,

			<341333333 0 0>,

			<384000000 0 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "cphy_rx_clk_src";

		clock-control-debugfs = "false";
@@ -859,12 +870,13 @@ 
			<&gcc GCC_CAMSS_OPE_CLK_SRC>,

			<&gcc GCC_CAMSS_OPE_CLK>;

		clock-rates =

			<171428571 200000000 200000000>,

			<171428571 266600000 266600000>,

			<240000000 465000000 465000000>,

			<240000000 580000000 580000000>;

			<171428571 200000000 0>,

			<171428571 266600000 0>,

			<240000000 465000000 0>,

			<240000000 576000000 0>;

		clock-cntl-level = "svs", "svs_l1", "nominal", "turbo";

		src-clock-name = "ope_clk_src";

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;

		status = "ok";

	};

};

arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-cpas.txt

+20 −5
Original line number Diff line number Diff line
@@ -67,9 +67,12 @@ First Level Node - CAM CPAS device 


- cam_hw_fuse

  Usage: optional

  Value type: <u32>

  Definition: List of fuse based features and respective

	fuse info.

  Value type: <u32:fuse_id> <u32:address> <u32:fuse_bit> <u32:fuse_type> <u32:hw_id>

   fuse_id: fuse id for each features

   address: fuse register io address

   fuse_bit: fuse bit number in the fuse registers

   fuse_type: fuse feature is enable type or disable type

   hw_id: Hw id of the feature



- custom-id

  Usage: optinal
@@ -133,6 +136,16 @@ First Level Node - CAM CPAS device 
  Definition: List of strings corresponds clock-rates levels.

  Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo.



- qcom,cam-cx-ipeak

  Usage: required

  Value type: <u32>

  Definition: Camera Cx Ipeak ID.



- qcom,cx-ipeak-gpu-limit;

  Usage: required

  Value type: <u32>

  Definition: Camera Cx Ipeak GPU Limit.



- control-camnoc-axi-clk

  Usage: optional

  Value type: <empty>
@@ -294,8 +307,8 @@ Example: 
		reg = <0xac40000 0x1000>,

			<0xac42000 0x5000>;

		reg-cam-base = <0x40000 0x42000>;

		cam_hw_fuse = <CAM_CPAS_QCFA_BINNING_ENABLE 0x00780210 29>,

			<CAM_CPAS_SECURE_CAMERA_ENABLE 0x00780210 18>;

		cam_hw_fuse = <CAM_CPAS_QCFA_BINNING_ENABLE 0x00780210 29  CAM_CPAS_FEATURE_TYPE_ENABLE 0>,

			<CAM_CPAS_SECURE_CAMERA_ENABLE 0x00780210 18 CAM_CPAS_FEATURE_TYPE_ENABLE 0>;

		interrupt-names = "cpas_camnoc";

		interrupts = <0 459 0>;

		qcom,cpas-hw-ver = <0x170100>; /* Titan v170 v1.0.0 */
@@ -316,6 +329,8 @@ Example: 
		src-clock-name = "slow_ahb_clk_src";

		clock-rates = <0 0 0 0 80000000 0>;

		clock-cntl-level = "turbo";

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;

		qcom,cx-ipeak-gpu-limit = <650000000>;

		control-camnoc-axi-clk;

		camnoc-bus-width = <32>;

		camnoc-axi-clk-bw-margin-perc = <10>;

arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-csiphy.txt

+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ First Level Node - CSIPHY device 
  Definition: Should be "qcom,csiphy-v1.0",

	"qcom,csiphy-v1.1", "qcom,csiphy-v1.2", "qcom,csiphy-v1.2.1",

	"qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", "qcom,csiphy-v1.2.2.2",

	"qcom,csiphy-v1.2.3", "qcom,csiphy".

	"qcom,csiphy-v1.2.3", "qcom,csiphy-v2.0.1", "qcom,csiphy".



- cell-index: csiphy hardware core index

  Usage: required