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Commit d614cb0b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC fixes from Olof Johansson:
 "A smaller set of fixes this week, and all regression fixes:
   - a handful of issues fixed on at91 with common clock conversion
   - a set of fixes for Marvell mvebu (SMP, coherency, PM)
   - a clock fix for i.MX6Q.
   - ... and a SMP/hotplug fix for Exynos"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: EXYNOS: Fix core ID used by platsmp and hotplug code
  ARM: at91/dt: add missing clocks property to pwm node in sam9x5.dtsi
  ARM: at91/dt: fix usb0 clocks definition in sam9n12 dtsi
  ARM: at91: at91sam9x5: correct typo error for ohci clock
  ARM: clk-imx6q: parent lvds_sel input from upstream clock gates
  ARM: mvebu: Fix coherency bus notifiers by using separate notifiers
  ARM: mvebu: Fix the operand list in the inline asm of armada_370_xp_pmsu_idle_enter
  ARM: mvebu: fix SMP boot for Armada 38x and Armada 375 Z1 in big endian
parents 1b9f0efd 9637f30e

arch/arm/boot/dts/at91sam9n12.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -925,7 +925,7 @@ 
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";

			reg = <0x00500000 0x00100000>;

			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;

			clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,

			clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,

				 <&uhpck>;

			clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";

			status = "disabled";

arch/arm/boot/dts/at91sam9x5.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -1124,6 +1124,7 @@ 
				compatible = "atmel,at91sam9rl-pwm";

				reg = <0xf8034000 0x300>;

				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;

				clocks = <&pwm_clk>;

				#pwm-cells = <3>;

				status = "disabled";

			};
@@ -1155,8 +1156,7 @@ 
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";

			reg = <0x00600000 0x100000>;

			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;

			clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,

				 <&uhpck>;

			clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;

			clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";

			status = "disabled";

		};

arch/arm/mach-exynos/hotplug.c

+6 −4
Original line number Diff line number Diff line
@@ -40,15 +40,17 @@ static inline void cpu_leave_lowpower(void) 


static inline void platform_do_lowpower(unsigned int cpu, int *spurious)

{

	u32 mpidr = cpu_logical_map(cpu);

	u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);



	for (;;) {



		/* make cpu1 to be turned off at next WFI command */

		if (cpu == 1)

			exynos_cpu_power_down(cpu);

		/* Turn the CPU off on next WFI instruction. */

		exynos_cpu_power_down(core_id);



		wfi();



		if (pen_release == cpu_logical_map(cpu)) {

		if (pen_release == core_id) {

			/*

			 * OK, proper wakeup, we're done

			 */

arch/arm/mach-exynos/platsmp.c

+19 −15
Original line number Diff line number Diff line
@@ -90,7 +90,8 @@ static void exynos_secondary_init(unsigned int cpu) 
static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)

{

	unsigned long timeout;

	unsigned long phys_cpu = cpu_logical_map(cpu);

	u32 mpidr = cpu_logical_map(cpu);

	u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);

	int ret = -ENOSYS;



	/*
@@ -104,17 +105,18 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) 
	 * the holding pen - release it, then wait for it to flag

	 * that it has been released by resetting pen_release.

	 *

	 * Note that "pen_release" is the hardware CPU ID, whereas

	 * Note that "pen_release" is the hardware CPU core ID, whereas

	 * "cpu" is Linux's internal ID.

	 */

	write_pen_release(phys_cpu);

	write_pen_release(core_id);



	if (!exynos_cpu_power_state(cpu)) {

		exynos_cpu_power_up(cpu);

	if (!exynos_cpu_power_state(core_id)) {

		exynos_cpu_power_up(core_id);

		timeout = 10;



		/* wait max 10 ms until cpu1 is on */

		while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {

		while (exynos_cpu_power_state(core_id)

		       != S5P_CORE_LOCAL_PWR_EN) {

			if (timeout-- == 0)

				break;
@@ -145,20 +147,20 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) 
		 * Try to set boot address using firmware first

		 * and fall back to boot register if it fails.

		 */

		ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);

		ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);

		if (ret && ret != -ENOSYS)

			goto fail;

		if (ret == -ENOSYS) {

			void __iomem *boot_reg = cpu_boot_reg(phys_cpu);

			void __iomem *boot_reg = cpu_boot_reg(core_id);



			if (IS_ERR(boot_reg)) {

				ret = PTR_ERR(boot_reg);

				goto fail;

			}

			__raw_writel(boot_addr, cpu_boot_reg(phys_cpu));

			__raw_writel(boot_addr, cpu_boot_reg(core_id));

		}



		call_firmware_op(cpu_boot, phys_cpu);

		call_firmware_op(cpu_boot, core_id);



		arch_send_wakeup_ipi_mask(cpumask_of(cpu));
@@ -227,22 +229,24 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) 
	 * boot register if it fails.

	 */

	for (i = 1; i < max_cpus; ++i) {

		unsigned long phys_cpu;

		unsigned long boot_addr;

		u32 mpidr;

		u32 core_id;

		int ret;



		phys_cpu = cpu_logical_map(i);

		mpidr = cpu_logical_map(i);

		core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);

		boot_addr = virt_to_phys(exynos4_secondary_startup);



		ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);

		ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);

		if (ret && ret != -ENOSYS)

			break;

		if (ret == -ENOSYS) {

			void __iomem *boot_reg = cpu_boot_reg(phys_cpu);

			void __iomem *boot_reg = cpu_boot_reg(core_id);



			if (IS_ERR(boot_reg))

				break;

			__raw_writel(boot_addr, cpu_boot_reg(phys_cpu));

			__raw_writel(boot_addr, cpu_boot_reg(core_id));

		}

	}

}

arch/arm/mach-imx/clk-imx6q.c

+2 −2
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ static const char *cko_sels[] = { "cko1", "cko2", }; 
static const char *lvds_sels[] = {

	"dummy", "dummy", "dummy", "dummy", "dummy", "dummy",

	"pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",

	"pcie_ref", "sata_ref",

	"pcie_ref_125m", "sata_ref_100m",

};



enum mx6q_clks {
@@ -491,7 +491,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 


	/* All existing boards with PCIe use LVDS1 */

	if (IS_ENABLED(CONFIG_PCI_IMX6))

		clk_set_parent(clk[lvds1_sel], clk[sata_ref]);

		clk_set_parent(clk[lvds1_sel], clk[sata_ref_100m]);



	/* Set initial power mode */

	imx6q_set_lpm(WAIT_CLOCKED);