Loading drivers/net/wireless/cnss2/pci.c +14 −0 Original line number Diff line number Diff line Loading @@ -62,12 +62,17 @@ static DEFINE_SPINLOCK(pci_link_down_lock); #define QCA6390_CE_COMMON_REG_BASE 0xA18000 #define QCA6390_CE_SRC_RING_BASE_LSB_OFFSET 0x0 #define QCA6390_CE_SRC_RING_BASE_MSB_OFFSET 0x4 #define QCA6390_CE_SRC_RING_ID_OFFSET 0x8 #define QCA6390_CE_SRC_RING_MISC_OFFSET 0x10 #define QCA6390_CE_SRC_CTRL_OFFSET 0x58 #define QCA6390_CE_SRC_R0_CE_CH_SRC_IS_OFFSET 0x5C #define QCA6390_CE_SRC_RING_HP_OFFSET 0x400 #define QCA6390_CE_SRC_RING_TP_OFFSET 0x404 #define QCA6390_CE_DEST_RING_BASE_LSB_OFFSET 0x0 #define QCA6390_CE_DEST_RING_BASE_MSB_OFFSET 0x4 #define QCA6390_CE_DEST_RING_ID_OFFSET 0x8 #define QCA6390_CE_DEST_RING_MISC_OFFSET 0x10 #define QCA6390_CE_DEST_CTRL_OFFSET 0xB0 #define QCA6390_CE_CH_DST_IS_OFFSET 0xB4 Loading @@ -76,6 +81,8 @@ static DEFINE_SPINLOCK(pci_link_down_lock); #define QCA6390_CE_DEST_RING_TP_OFFSET 0x404 #define QCA6390_CE_STATUS_RING_BASE_LSB_OFFSET 0x58 #define QCA6390_CE_STATUS_RING_BASE_MSB_OFFSET 0x5C #define QCA6390_CE_STATUS_RING_ID_OFFSET 0x60 #define QCA6390_CE_STATUS_RING_MISC_OFFSET 0x68 #define QCA6390_CE_STATUS_RING_HP_OFFSET 0x408 #define QCA6390_CE_STATUS_RING_TP_OFFSET 0x40C Loading Loading @@ -104,8 +111,11 @@ static DEFINE_SPINLOCK(pci_link_down_lock); static struct cnss_pci_reg ce_src[] = { { "SRC_RING_BASE_LSB", QCA6390_CE_SRC_RING_BASE_LSB_OFFSET }, { "SRC_RING_BASE_MSB", QCA6390_CE_SRC_RING_BASE_MSB_OFFSET }, { "SRC_RING_ID", QCA6390_CE_SRC_RING_ID_OFFSET }, { "SRC_RING_MISC", QCA6390_CE_SRC_RING_MISC_OFFSET }, { "SRC_CTRL", QCA6390_CE_SRC_CTRL_OFFSET }, { "SRC_R0_CE_CH_SRC_IS", QCA6390_CE_SRC_R0_CE_CH_SRC_IS_OFFSET }, { "SRC_RING_HP", QCA6390_CE_SRC_RING_HP_OFFSET }, { "SRC_RING_TP", QCA6390_CE_SRC_RING_TP_OFFSET }, { NULL }, Loading @@ -113,6 +123,8 @@ static struct cnss_pci_reg ce_src[] = { static struct cnss_pci_reg ce_dst[] = { { "DEST_RING_BASE_LSB", QCA6390_CE_DEST_RING_BASE_LSB_OFFSET }, { "DEST_RING_BASE_MSB", QCA6390_CE_DEST_RING_BASE_MSB_OFFSET }, { "DEST_RING_ID", QCA6390_CE_DEST_RING_ID_OFFSET }, { "DEST_RING_MISC", QCA6390_CE_DEST_RING_MISC_OFFSET }, { "DEST_CTRL", QCA6390_CE_DEST_CTRL_OFFSET }, { "CE_CH_DST_IS", QCA6390_CE_CH_DST_IS_OFFSET }, Loading @@ -120,6 +132,8 @@ static struct cnss_pci_reg ce_dst[] = { { "DEST_RING_HP", QCA6390_CE_DEST_RING_HP_OFFSET }, { "DEST_RING_TP", QCA6390_CE_DEST_RING_TP_OFFSET }, { "STATUS_RING_BASE_LSB", QCA6390_CE_STATUS_RING_BASE_LSB_OFFSET }, { "STATUS_RING_BASE_MSB", QCA6390_CE_STATUS_RING_BASE_MSB_OFFSET }, { "STATUS_RING_ID", QCA6390_CE_STATUS_RING_ID_OFFSET }, { "STATUS_RING_MISC", QCA6390_CE_STATUS_RING_MISC_OFFSET }, { "STATUS_RING_HP", QCA6390_CE_STATUS_RING_HP_OFFSET }, { "STATUS_RING_TP", QCA6390_CE_STATUS_RING_TP_OFFSET }, Loading Loading
drivers/net/wireless/cnss2/pci.c +14 −0 Original line number Diff line number Diff line Loading @@ -62,12 +62,17 @@ static DEFINE_SPINLOCK(pci_link_down_lock); #define QCA6390_CE_COMMON_REG_BASE 0xA18000 #define QCA6390_CE_SRC_RING_BASE_LSB_OFFSET 0x0 #define QCA6390_CE_SRC_RING_BASE_MSB_OFFSET 0x4 #define QCA6390_CE_SRC_RING_ID_OFFSET 0x8 #define QCA6390_CE_SRC_RING_MISC_OFFSET 0x10 #define QCA6390_CE_SRC_CTRL_OFFSET 0x58 #define QCA6390_CE_SRC_R0_CE_CH_SRC_IS_OFFSET 0x5C #define QCA6390_CE_SRC_RING_HP_OFFSET 0x400 #define QCA6390_CE_SRC_RING_TP_OFFSET 0x404 #define QCA6390_CE_DEST_RING_BASE_LSB_OFFSET 0x0 #define QCA6390_CE_DEST_RING_BASE_MSB_OFFSET 0x4 #define QCA6390_CE_DEST_RING_ID_OFFSET 0x8 #define QCA6390_CE_DEST_RING_MISC_OFFSET 0x10 #define QCA6390_CE_DEST_CTRL_OFFSET 0xB0 #define QCA6390_CE_CH_DST_IS_OFFSET 0xB4 Loading @@ -76,6 +81,8 @@ static DEFINE_SPINLOCK(pci_link_down_lock); #define QCA6390_CE_DEST_RING_TP_OFFSET 0x404 #define QCA6390_CE_STATUS_RING_BASE_LSB_OFFSET 0x58 #define QCA6390_CE_STATUS_RING_BASE_MSB_OFFSET 0x5C #define QCA6390_CE_STATUS_RING_ID_OFFSET 0x60 #define QCA6390_CE_STATUS_RING_MISC_OFFSET 0x68 #define QCA6390_CE_STATUS_RING_HP_OFFSET 0x408 #define QCA6390_CE_STATUS_RING_TP_OFFSET 0x40C Loading Loading @@ -104,8 +111,11 @@ static DEFINE_SPINLOCK(pci_link_down_lock); static struct cnss_pci_reg ce_src[] = { { "SRC_RING_BASE_LSB", QCA6390_CE_SRC_RING_BASE_LSB_OFFSET }, { "SRC_RING_BASE_MSB", QCA6390_CE_SRC_RING_BASE_MSB_OFFSET }, { "SRC_RING_ID", QCA6390_CE_SRC_RING_ID_OFFSET }, { "SRC_RING_MISC", QCA6390_CE_SRC_RING_MISC_OFFSET }, { "SRC_CTRL", QCA6390_CE_SRC_CTRL_OFFSET }, { "SRC_R0_CE_CH_SRC_IS", QCA6390_CE_SRC_R0_CE_CH_SRC_IS_OFFSET }, { "SRC_RING_HP", QCA6390_CE_SRC_RING_HP_OFFSET }, { "SRC_RING_TP", QCA6390_CE_SRC_RING_TP_OFFSET }, { NULL }, Loading @@ -113,6 +123,8 @@ static struct cnss_pci_reg ce_src[] = { static struct cnss_pci_reg ce_dst[] = { { "DEST_RING_BASE_LSB", QCA6390_CE_DEST_RING_BASE_LSB_OFFSET }, { "DEST_RING_BASE_MSB", QCA6390_CE_DEST_RING_BASE_MSB_OFFSET }, { "DEST_RING_ID", QCA6390_CE_DEST_RING_ID_OFFSET }, { "DEST_RING_MISC", QCA6390_CE_DEST_RING_MISC_OFFSET }, { "DEST_CTRL", QCA6390_CE_DEST_CTRL_OFFSET }, { "CE_CH_DST_IS", QCA6390_CE_CH_DST_IS_OFFSET }, Loading @@ -120,6 +132,8 @@ static struct cnss_pci_reg ce_dst[] = { { "DEST_RING_HP", QCA6390_CE_DEST_RING_HP_OFFSET }, { "DEST_RING_TP", QCA6390_CE_DEST_RING_TP_OFFSET }, { "STATUS_RING_BASE_LSB", QCA6390_CE_STATUS_RING_BASE_LSB_OFFSET }, { "STATUS_RING_BASE_MSB", QCA6390_CE_STATUS_RING_BASE_MSB_OFFSET }, { "STATUS_RING_ID", QCA6390_CE_STATUS_RING_ID_OFFSET }, { "STATUS_RING_MISC", QCA6390_CE_STATUS_RING_MISC_OFFSET }, { "STATUS_RING_HP", QCA6390_CE_STATUS_RING_HP_OFFSET }, { "STATUS_RING_TP", QCA6390_CE_STATUS_RING_TP_OFFSET }, Loading