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Commit d59095f7 authored by Andres Rodriguez's avatar Andres Rodriguez Committed by Alex Deucher
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drm/radeon: take ownership of pipe initialization 



Take ownership of pipe initialization away from KFD.

Note that hpd_eop_gpu_addr was already large enough to accomodate all
pipes.

Reviewed-by: default avatarEdward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAndres Rodriguez <andresx7@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dc102c43

drivers/gpu/drm/radeon/cik.c

+14 −13
Original line number Diff line number Diff line
@@ -4580,10 +4580,10 @@ static int cik_cp_compute_resume(struct radeon_device *rdev) 
	/* init the pipes */

	mutex_lock(&rdev->srbm_mutex);



	eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr;



	cik_srbm_select(rdev, 0, 0, 0, 0);

	for (i = 0; i < rdev->mec.num_pipe; ++i) {

		cik_srbm_select(rdev, 0, i, 0, 0);



		eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2) ;

		/* write the EOP addr */

		WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);

		WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
@@ -4597,6 +4597,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev) 
		tmp |= order_base_2(MEC_HPD_SIZE / 8);

		WREG32(CP_HPD_EOP_CONTROL, tmp);



	}

	mutex_unlock(&rdev->srbm_mutex);



	/* init the queues.  Just two for now. */

drivers/gpu/drm/radeon/radeon_kfd.c

+1 −12
Original line number Diff line number Diff line
@@ -423,18 +423,7 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 
static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,

				uint32_t hpd_size, uint64_t hpd_gpu_addr)

{

	uint32_t mec = (pipe_id / CIK_PIPE_PER_MEC) + 1;

	uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);



	lock_srbm(kgd, mec, pipe, 0, 0);

	write_register(kgd, CP_HPD_EOP_BASE_ADDR,

			lower_32_bits(hpd_gpu_addr >> 8));

	write_register(kgd, CP_HPD_EOP_BASE_ADDR_HI,

			upper_32_bits(hpd_gpu_addr >> 8));

	write_register(kgd, CP_HPD_EOP_VMID, 0);

	write_register(kgd, CP_HPD_EOP_CONTROL, hpd_size);

	unlock_srbm(kgd);



	/* nothing to do here */

	return 0;

}