Loading arch/arc/Kconfig +1 −1 Original line number Diff line number Diff line Loading @@ -413,7 +413,7 @@ config ARC_HAS_RTC default n depends on !SMP config ARC_HAS_GRTC config ARC_HAS_GFRC bool "SMP synchronized 64-bit cycle counter" default y depends on SMP Loading arch/arc/configs/vdk_hs38_smp_defconfig +1 −1 Original line number Diff line number Diff line Loading @@ -16,7 +16,7 @@ CONFIG_ARC_PLAT_AXS10X=y CONFIG_AXS103=y CONFIG_ISA_ARCV2=y CONFIG_SMP=y # CONFIG_ARC_HAS_GRTC is not set # CONFIG_ARC_HAS_GFRC is not set CONFIG_ARC_UBOOT_SUPPORT=y CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp" CONFIG_PREEMPT=y Loading arch/arc/include/asm/mcip.h +2 −2 Original line number Diff line number Diff line Loading @@ -39,8 +39,8 @@ struct mcip_cmd { #define CMD_DEBUG_SET_MASK 0x34 #define CMD_DEBUG_SET_SELECT 0x36 #define CMD_GRTC_READ_LO 0x42 #define CMD_GRTC_READ_HI 0x43 #define CMD_GFRC_READ_LO 0x42 #define CMD_GFRC_READ_HI 0x43 #define CMD_IDU_ENABLE 0x71 #define CMD_IDU_DISABLE 0x72 Loading arch/arc/kernel/mcip.c +5 −5 Original line number Diff line number Diff line Loading @@ -96,13 +96,13 @@ static void mcip_probe_n_setup(void) #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad3:8, idu:1, llm:1, num_cores:6, iocoh:1, grtc:1, dbg:1, pad2:1, iocoh:1, gfrc:1, dbg:1, pad2:1, msg:1, sem:1, ipi:1, pad:1, ver:8; #else unsigned int ver:8, pad:1, ipi:1, sem:1, msg:1, pad2:1, dbg:1, grtc:1, iocoh:1, pad2:1, dbg:1, gfrc:1, iocoh:1, num_cores:6, llm:1, idu:1, pad3:8; #endif Loading @@ -116,7 +116,7 @@ static void mcip_probe_n_setup(void) IS_AVAIL1(mp.ipi, "IPI "), IS_AVAIL1(mp.idu, "IDU "), IS_AVAIL1(mp.dbg, "DEBUG "), IS_AVAIL1(mp.grtc, "GRTC")); IS_AVAIL1(mp.gfrc, "GFRC")); idu_detected = mp.idu; Loading @@ -125,8 +125,8 @@ static void mcip_probe_n_setup(void) __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf); } if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc) panic("kernel trying to use non-existent GRTC\n"); if (IS_ENABLED(CONFIG_ARC_HAS_GFRC) && !mp.gfrc) panic("kernel trying to use non-existent GFRC\n"); } struct plat_smp_ops plat_smp_ops = { Loading arch/arc/kernel/time.c +4 −4 Original line number Diff line number Diff line Loading @@ -62,7 +62,7 @@ /********** Clock Source Device *********/ #ifdef CONFIG_ARC_HAS_GRTC #ifdef CONFIG_ARC_HAS_GFRC static int arc_counter_setup(void) { Loading @@ -83,10 +83,10 @@ static cycle_t arc_counter_read(struct clocksource *cs) local_irq_save(flags); __mcip_cmd(CMD_GRTC_READ_LO, 0); __mcip_cmd(CMD_GFRC_READ_LO, 0); stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK); __mcip_cmd(CMD_GRTC_READ_HI, 0); __mcip_cmd(CMD_GFRC_READ_HI, 0); stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK); local_irq_restore(flags); Loading @@ -95,7 +95,7 @@ static cycle_t arc_counter_read(struct clocksource *cs) } static struct clocksource arc_counter = { .name = "ARConnect GRTC", .name = "ARConnect GFRC", .rating = 400, .read = arc_counter_read, .mask = CLOCKSOURCE_MASK(64), Loading Loading
arch/arc/Kconfig +1 −1 Original line number Diff line number Diff line Loading @@ -413,7 +413,7 @@ config ARC_HAS_RTC default n depends on !SMP config ARC_HAS_GRTC config ARC_HAS_GFRC bool "SMP synchronized 64-bit cycle counter" default y depends on SMP Loading
arch/arc/configs/vdk_hs38_smp_defconfig +1 −1 Original line number Diff line number Diff line Loading @@ -16,7 +16,7 @@ CONFIG_ARC_PLAT_AXS10X=y CONFIG_AXS103=y CONFIG_ISA_ARCV2=y CONFIG_SMP=y # CONFIG_ARC_HAS_GRTC is not set # CONFIG_ARC_HAS_GFRC is not set CONFIG_ARC_UBOOT_SUPPORT=y CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp" CONFIG_PREEMPT=y Loading
arch/arc/include/asm/mcip.h +2 −2 Original line number Diff line number Diff line Loading @@ -39,8 +39,8 @@ struct mcip_cmd { #define CMD_DEBUG_SET_MASK 0x34 #define CMD_DEBUG_SET_SELECT 0x36 #define CMD_GRTC_READ_LO 0x42 #define CMD_GRTC_READ_HI 0x43 #define CMD_GFRC_READ_LO 0x42 #define CMD_GFRC_READ_HI 0x43 #define CMD_IDU_ENABLE 0x71 #define CMD_IDU_DISABLE 0x72 Loading
arch/arc/kernel/mcip.c +5 −5 Original line number Diff line number Diff line Loading @@ -96,13 +96,13 @@ static void mcip_probe_n_setup(void) #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad3:8, idu:1, llm:1, num_cores:6, iocoh:1, grtc:1, dbg:1, pad2:1, iocoh:1, gfrc:1, dbg:1, pad2:1, msg:1, sem:1, ipi:1, pad:1, ver:8; #else unsigned int ver:8, pad:1, ipi:1, sem:1, msg:1, pad2:1, dbg:1, grtc:1, iocoh:1, pad2:1, dbg:1, gfrc:1, iocoh:1, num_cores:6, llm:1, idu:1, pad3:8; #endif Loading @@ -116,7 +116,7 @@ static void mcip_probe_n_setup(void) IS_AVAIL1(mp.ipi, "IPI "), IS_AVAIL1(mp.idu, "IDU "), IS_AVAIL1(mp.dbg, "DEBUG "), IS_AVAIL1(mp.grtc, "GRTC")); IS_AVAIL1(mp.gfrc, "GFRC")); idu_detected = mp.idu; Loading @@ -125,8 +125,8 @@ static void mcip_probe_n_setup(void) __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf); } if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc) panic("kernel trying to use non-existent GRTC\n"); if (IS_ENABLED(CONFIG_ARC_HAS_GFRC) && !mp.gfrc) panic("kernel trying to use non-existent GFRC\n"); } struct plat_smp_ops plat_smp_ops = { Loading
arch/arc/kernel/time.c +4 −4 Original line number Diff line number Diff line Loading @@ -62,7 +62,7 @@ /********** Clock Source Device *********/ #ifdef CONFIG_ARC_HAS_GRTC #ifdef CONFIG_ARC_HAS_GFRC static int arc_counter_setup(void) { Loading @@ -83,10 +83,10 @@ static cycle_t arc_counter_read(struct clocksource *cs) local_irq_save(flags); __mcip_cmd(CMD_GRTC_READ_LO, 0); __mcip_cmd(CMD_GFRC_READ_LO, 0); stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK); __mcip_cmd(CMD_GRTC_READ_HI, 0); __mcip_cmd(CMD_GFRC_READ_HI, 0); stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK); local_irq_restore(flags); Loading @@ -95,7 +95,7 @@ static cycle_t arc_counter_read(struct clocksource *cs) } static struct clocksource arc_counter = { .name = "ARConnect GRTC", .name = "ARConnect GFRC", .rating = 400, .read = arc_counter_read, .mask = CLOCKSOURCE_MASK(64), Loading