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Commit d58086de authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nv40-50/gr: restructure grctx/prog generation 



The conditional definition of the generation helper functions apparently
confuses some IDEs....

Reported-by: default avatarMarcin Slusarz <marcin.slusarz@gmail.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent a8f81837

drivers/gpu/drm/nouveau/nouveau_drv.h

+4 −2
Original line number Diff line number Diff line
@@ -1286,13 +1286,15 @@ extern int nv20_graph_create(struct drm_device *); 


/* nv40_graph.c */

extern int  nv40_graph_create(struct drm_device *);

extern void nv40_grctx_init(struct nouveau_grctx *);

extern void nv40_grctx_init(struct drm_device *, u32 *size);

extern void nv40_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);



/* nv50_graph.c */

extern int  nv50_graph_create(struct drm_device *);

extern int  nv50_grctx_init(struct nouveau_grctx *);

extern struct nouveau_enum nv50_data_error_names[];

extern int  nv50_graph_isr_chid(struct drm_device *dev, u64 inst);

extern int  nv50_grctx_init(struct drm_device *, u32 *, u32, u32 *, u32 *);

extern void nv50_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);



/* nvc0_graph.c */

extern int  nvc0_graph_create(struct drm_device *);

drivers/gpu/drm/nouveau/nouveau_grctx.h

+0 −4
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ struct nouveau_grctx { 
	uint32_t ctxvals_base;

};



#ifdef CP_CTX

static inline void

cp_out(struct nouveau_grctx *ctx, uint32_t inst)

{
@@ -88,10 +87,8 @@ _cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name) 
		    (state ? 0 : CP_BRA_IF_CLEAR));

}

#define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)

#ifdef CP_BRA_MOD

#define cp_cal(c, f, s, n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n)

#define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)

#endif



static inline void

_cp_wait(struct nouveau_grctx *ctx, int flag, int state)
@@ -128,6 +125,5 @@ gr_def(struct nouveau_grctx *ctx, uint32_t reg, uint32_t val) 


	nv_wo32(ctx->data, reg * 4, val);

}

#endif



#endif

drivers/gpu/drm/nouveau/nv40_graph.c

+4 −25
Original line number Diff line number Diff line
@@ -27,7 +27,6 @@ 
#include "drmP.h"

#include "drm.h"

#include "nouveau_drv.h"

#include "nouveau_grctx.h"

#include "nouveau_ramht.h"



struct nv40_graph_engine {
@@ -42,7 +41,6 @@ nv40_graph_context_new(struct nouveau_channel *chan, int engine) 
	struct drm_device *dev = chan->dev;

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_gpuobj *grctx = NULL;

	struct nouveau_grctx ctx = {};

	unsigned long flags;

	int ret;
@@ -52,11 +50,7 @@ nv40_graph_context_new(struct nouveau_channel *chan, int engine) 
		return ret;



	/* Initialise default context values */

	ctx.dev = chan->dev;

	ctx.mode = NOUVEAU_GRCTX_VALS;

	ctx.data = grctx;

	nv40_grctx_init(&ctx);



	nv40_grctx_fill(dev, grctx);

	nv_wo32(grctx, 0, grctx->vinst);



	/* init grctx pointer in ramfc, and on PFIFO if channel is
@@ -184,8 +178,7 @@ nv40_graph_init(struct drm_device *dev, int engine) 
	struct nv40_graph_engine *pgraph = nv_engine(dev, engine);

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;

	struct nouveau_grctx ctx = {};

	uint32_t vramsz, *cp;

	uint32_t vramsz;

	int i, j;



	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
@@ -193,22 +186,8 @@ nv40_graph_init(struct drm_device *dev, int engine) 
	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |

			 NV_PMC_ENABLE_PGRAPH);



	cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);

	if (!cp)

		return -ENOMEM;



	ctx.dev = dev;

	ctx.mode = NOUVEAU_GRCTX_PROG;

	ctx.data = cp;

	ctx.ctxprog_max = 256;

	nv40_grctx_init(&ctx);

	pgraph->grctx_size = ctx.ctxvals_pos * 4;



	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);

	for (i = 0; i < ctx.ctxprog_len; i++)

		nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);



	kfree(cp);

	/* generate and upload context program */

	nv40_grctx_init(dev, &pgraph->grctx_size);



	/* No context present currently */

	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);

drivers/gpu/drm/nouveau/nv40_grctx.c

+30 −2
Original line number Diff line number Diff line
@@ -595,8 +595,8 @@ nv40_graph_construct_shader(struct nouveau_grctx *ctx) 
	}

}



void

nv40_grctx_init(struct nouveau_grctx *ctx)

static void

nv40_grctx_generate(struct nouveau_grctx *ctx)

{

	/* decide whether we're loading/unloading the context */

	cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
@@ -660,3 +660,31 @@ nv40_grctx_init(struct nouveau_grctx *ctx) 
	cp_out (ctx, CP_END);

}



void

nv40_grctx_fill(struct drm_device *dev, struct nouveau_gpuobj *mem)

{

	nv40_grctx_generate(&(struct nouveau_grctx) {

			     .dev = dev,

			     .mode = NOUVEAU_GRCTX_VALS,

			     .data = mem,

			   });

}



void

nv40_grctx_init(struct drm_device *dev, u32 *size)

{

	u32 ctxprog[256], i;

	struct nouveau_grctx ctx = {

		.dev = dev,

		.mode = NOUVEAU_GRCTX_PROG,

		.data = ctxprog,

		.ctxprog_max = ARRAY_SIZE(ctxprog)

	};



	nv40_grctx_generate(&ctx);



	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);

	for (i = 0; i < ctx.ctxprog_len; i++)

		nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, ctxprog[i]);

	*size = ctx.ctxvals_pos * 4;

}

drivers/gpu/drm/nouveau/nv50_graph.c

+4 −17
Original line number Diff line number Diff line
@@ -28,7 +28,6 @@ 
#include "drm.h"

#include "nouveau_drv.h"

#include "nouveau_ramht.h"

#include "nouveau_grctx.h"

#include "nouveau_dma.h"

#include "nouveau_vm.h"

#include "nv50_evo.h"
@@ -229,7 +228,6 @@ nv50_graph_context_new(struct nouveau_channel *chan, int engine) 
	struct nouveau_gpuobj *ramin = chan->ramin;

	struct nouveau_gpuobj *grctx = NULL;

	struct nv50_graph_engine *pgraph = nv_engine(dev, engine);

	struct nouveau_grctx ctx = {};

	int hdr, ret;



	NV_DEBUG(dev, "ch%d\n", chan->id);
@@ -248,11 +246,7 @@ nv50_graph_context_new(struct nouveau_channel *chan, int engine) 
	nv_wo32(ramin, hdr + 0x10, 0);

	nv_wo32(ramin, hdr + 0x14, 0x00010000);



	ctx.dev = chan->dev;

	ctx.mode = NOUVEAU_GRCTX_VALS;

	ctx.data = grctx;

	nv50_grctx_init(&ctx);



	nv50_grctx_fill(dev, grctx);

	nv_wo32(grctx, 0x00000, chan->ramin->vinst >> 12);



	dev_priv->engine.instmem.flush(dev);
@@ -996,28 +990,21 @@ nv50_graph_create(struct drm_device *dev) 
{

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nv50_graph_engine *pgraph;

	struct nouveau_grctx ctx = {};

	int ret;



	pgraph = kzalloc(sizeof(*pgraph),GFP_KERNEL);

	if (!pgraph)

		return -ENOMEM;



	ctx.dev = dev;

	ctx.mode = NOUVEAU_GRCTX_PROG;

	ctx.data = pgraph->ctxprog;

	ctx.ctxprog_max = ARRAY_SIZE(pgraph->ctxprog);



	ret = nv50_grctx_init(&ctx);

	ret = nv50_grctx_init(dev, pgraph->ctxprog, ARRAY_SIZE(pgraph->ctxprog),

				  &pgraph->ctxprog_size,

				  &pgraph->grctx_size);

	if (ret) {

		NV_ERROR(dev, "PGRAPH: ctxprog build failed\n");

		kfree(pgraph);

		return 0;

	}



	pgraph->grctx_size = ctx.ctxvals_pos * 4;

	pgraph->ctxprog_size = ctx.ctxprog_len;



	pgraph->base.destroy = nv50_graph_destroy;

	pgraph->base.init = nv50_graph_init;

	pgraph->base.fini = nv50_graph_fini;