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Commit d522ae1e authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
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powerpc/mm: Batch tlb flush when invalidating pte entries 



This will improve the task exit case, by batching tlb invalidates.

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent e58d1cf2

arch/powerpc/include/asm/book3s/64/radix.h

+10 −3
Original line number Diff line number Diff line
@@ -140,13 +140,20 @@ static inline unsigned long radix__pte_update(struct mm_struct *mm, 
		unsigned long new_pte;



		old_pte = __radix_pte_update(ptep, ~0, 0);

		asm volatile("ptesync" : : : "memory");

		/*

		 * new value of pte

		 */

		new_pte = (old_pte | set) & ~clr;

		/*

		 * If we are trying to clear the pte, we can skip

		 * the below sequence and batch the tlb flush. The

		 * tlb flush batching is done by mmu gather code

		 */

		if (new_pte) {

			asm volatile("ptesync" : : : "memory");

			radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr);

			__radix_pte_update(ptep, 0, new_pte);

		}

	} else

		old_pte = __radix_pte_update(ptep, clr, set);

	asm volatile("ptesync" : : : "memory");