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Commit d4be2f1b authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Simon Horman
Browse files

ARM: dts: r8a73a4: Rename the serial port clock to fck 



The clock is really the device functional clock, not the interface
clock. Rename it.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 92489120

arch/arm/boot/dts/r8a73a4.dtsi

+6 −6
Original line number Original line Diff line number Diff line
@@ -335,7 +335,7 @@ 
		reg = <0 0xe6c20000 0 0x100>;

		reg = <0 0xe6c20000 0 0x100>;

		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;

		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&pd_a3sp>;

		power-domains = <&pd_a3sp>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -345,7 +345,7 @@ 
		reg = <0 0xe6c30000 0 0x100>;

		reg = <0 0xe6c30000 0 0x100>;

		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;

		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&pd_a3sp>;

		power-domains = <&pd_a3sp>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -355,7 +355,7 @@ 
		reg = <0 0xe6c40000 0 0x100>;

		reg = <0 0xe6c40000 0 0x100>;

		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;

		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&pd_a3sp>;

		power-domains = <&pd_a3sp>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -365,7 +365,7 @@ 
		reg = <0 0xe6c50000 0 0x100>;

		reg = <0 0xe6c50000 0 0x100>;

		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;

		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&pd_a3sp>;

		power-domains = <&pd_a3sp>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -375,7 +375,7 @@ 
		reg = <0 0xe6ce0000 0 0x100>;

		reg = <0 0xe6ce0000 0 0x100>;

		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;

		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&pd_a3sp>;

		power-domains = <&pd_a3sp>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -385,7 +385,7 @@ 
		reg = <0 0xe6cf0000 0 0x100>;

		reg = <0 0xe6cf0000 0 0x100>;

		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;

		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;

		clock-names = "sci_ick";

		clock-names = "fck";

		power-domains = <&pd_c4>;

		power-domains = <&pd_c4>;

		status = "disabled";

		status = "disabled";

	};

	};