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Commit d3f16750 authored by Laxminath Kasam's avatar Laxminath Kasam
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asoc: codecs: Update dmic2 support on WCD938x 



As DMIC2 is muxed on same channel with MBHC
on soundwire port3 of WCD938x codec, need to set
selection bit for DMIC2 during recording usecase
over it.

Change-Id: Ice9b92eb964af25e47db4b3d8d25db07a82a9bf2
Signed-off-by: default avatarLaxminath Kasam <lkasam@codeaurora.org>
parent 549d11d4

asoc/codecs/wcd938x/wcd938x.c

+8 −0
Original line number Diff line number Diff line
@@ -1126,6 +1126,7 @@ static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 
	u8 dmic_ctl_shift = 0;

	u8 dmic_clk_shift = 0;

	u8 dmic_clk_mask = 0;

	u16 dmic2_left_en = 0;



	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,

		w->name, event);
@@ -1141,6 +1142,7 @@ static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 
		dmic_ctl_shift = 0x00;

		break;

	case 2:

		dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;

	case 3:

		dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);

		dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
@@ -1182,6 +1184,9 @@ static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 
				(0x01 << dmic_ctl_shift), 0x00);

		/* 250us sleep as per HW requirement */

		usleep_range(250, 260);

		if (dmic2_left_en)

			snd_soc_component_update_bits(component,

				dmic2_left_en, 0x80, 0x80);

		/* Setting DMIC clock rate to 2.4MHz */

		snd_soc_component_update_bits(component,

					      dmic_clk_reg, dmic_clk_mask,
@@ -1199,6 +1204,9 @@ static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 
				WCD938X_DIGITAL_CDC_AMIC_CTL,

				(0x01 << dmic_ctl_shift),

				(0x01 << dmic_ctl_shift));

		if (dmic2_left_en)

			snd_soc_component_update_bits(component,

				dmic2_left_en, 0x80, 0x00);

		snd_soc_component_update_bits(component,

					      dmic_clk_en_reg, 0x08, 0x00);

		break;