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Commit d3d57927 authored by Kelvin Gardiner's avatar Kelvin Gardiner Committed by Mika Kuoppala
Browse files

drm/i915/icl: Update subslice define for ICL 11 



ICL 11 has a greater number of maximum subslices. This patch
reflects this.

v2: GEN11 updates to MCR_SELECTOR (Oscar)
v3: Copypasta error in the new defines (Lionel)

Bspec: 21139
BSpec: 21108

Signed-off-by: default avatarKelvin Gardiner <kelvin.gardiner@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com> (v1)
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> (v1)
Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Reviewed-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180316121456.11577-3-mika.kuoppala@linux.intel.com


Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
parent d53d5ffb

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -2151,6 +2151,10 @@ enum i915_power_well_id { 
#define   GEN8_MCR_SLICE_MASK		GEN8_MCR_SLICE(3)

#define   GEN8_MCR_SUBSLICE(subslice)	(((subslice) & 3) << 24)

#define   GEN8_MCR_SUBSLICE_MASK	GEN8_MCR_SUBSLICE(3)

#define   GEN11_MCR_SLICE(slice)	(((slice) & 0xf) << 27)

#define   GEN11_MCR_SLICE_MASK		GEN11_MCR_SLICE(0xf)

#define   GEN11_MCR_SUBSLICE(subslice)	(((subslice) & 0x7) << 24)

#define   GEN11_MCR_SUBSLICE_MASK	GEN11_MCR_SUBSLICE(0x7)

#define RING_IPEIR(base)	_MMIO((base)+0x64)

#define RING_IPEHR(base)	_MMIO((base)+0x68)

/*

drivers/gpu/drm/i915/intel_engine_cs.c

+18 −4
Original line number Diff line number Diff line
@@ -800,10 +800,24 @@ static inline uint32_t 
read_subslice_reg(struct drm_i915_private *dev_priv, int slice,

		  int subslice, i915_reg_t reg)

{

	uint32_t mcr_slice_subslice_mask;

	uint32_t mcr_slice_subslice_select;

	uint32_t mcr;

	uint32_t ret;

	enum forcewake_domains fw_domains;



	if (INTEL_GEN(dev_priv) >= 11) {

		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |

					  GEN11_MCR_SUBSLICE_MASK;

		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |

					    GEN11_MCR_SUBSLICE(subslice);

	} else {

		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |

					  GEN8_MCR_SUBSLICE_MASK;

		mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |

					    GEN8_MCR_SUBSLICE(subslice);

	}



	fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,

						    FW_REG_READ);

	fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
@@ -818,14 +832,14 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice, 
	 * The HW expects the slice and sublice selectors to be reset to 0

	 * after reading out the registers.

	 */

	WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));

	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);

	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);

	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);

	mcr &= ~mcr_slice_subslice_mask;

	mcr |= mcr_slice_subslice_select;

	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);



	ret = I915_READ_FW(reg);



	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);

	mcr &= ~mcr_slice_subslice_mask;

	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);



	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);

drivers/gpu/drm/i915/intel_ringbuffer.h

+1 −1
Original line number Diff line number Diff line
@@ -86,7 +86,7 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a) 
}



#define I915_MAX_SLICES	3

#define I915_MAX_SUBSLICES 3

#define I915_MAX_SUBSLICES 8



#define instdone_slice_mask(dev_priv__) \

	(INTEL_GEN(dev_priv__) == 7 ? \