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Commit d3703082 authored by leilk.liu's avatar leilk.liu Committed by Greg Kroah-Hartman
Browse files

spi: mediatek: use correct SPI_CFG2_REG MACRO 



[ Upstream commit 44b37eb79e16a56cb30ba55b2da452396b941e7a ]

this patch use correct SPI_CFG2_REG offset.

Signed-off-by: default avatarleilk.liu <leilk.liu@mediatek.com>
Link: https://lore.kernel.org/r/20200701090020.7935-1-leilk.liu@mediatek.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent e8af9e4d

drivers/spi/spi-mt65xx.c

+8 −7
Original line number Diff line number Diff line
@@ -41,7 +41,6 @@ 
#define SPI_CFG0_SCK_LOW_OFFSET           8

#define SPI_CFG0_CS_HOLD_OFFSET           16

#define SPI_CFG0_CS_SETUP_OFFSET          24

#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET    16

#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET    0

#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET   16
@@ -53,6 +52,8 @@ 
#define SPI_CFG1_CS_IDLE_MASK             0xff

#define SPI_CFG1_PACKET_LOOP_MASK         0xff00

#define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000

#define SPI_CFG2_SCK_HIGH_OFFSET          0

#define SPI_CFG2_SCK_LOW_OFFSET           16



#define SPI_CMD_ACT                  BIT(0)

#define SPI_CMD_RESUME               BIT(1)
@@ -259,7 +260,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable) 
static void mtk_spi_prepare_transfer(struct spi_master *master,

				     struct spi_transfer *xfer)

{

	u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;

	u32 spi_clk_hz, div, sck_time, cs_time, reg_val;

	struct mtk_spi *mdata = spi_master_get_devdata(master);



	spi_clk_hz = clk_get_rate(mdata->spi_clk);
@@ -272,18 +273,18 @@ static void mtk_spi_prepare_transfer(struct spi_master *master, 
	cs_time = sck_time * 2;



	if (mdata->dev_comp->enhance_timing) {

		reg_val = (((sck_time - 1) & 0xffff)

			   << SPI_CFG2_SCK_HIGH_OFFSET);

		reg_val |= (((sck_time - 1) & 0xffff)

			   << SPI_CFG0_SCK_HIGH_OFFSET);

		reg_val |= (((sck_time - 1) & 0xffff)

			   << SPI_ADJUST_CFG0_SCK_LOW_OFFSET);

			   << SPI_CFG2_SCK_LOW_OFFSET);

		writel(reg_val, mdata->base + SPI_CFG2_REG);

		reg_val |= (((cs_time - 1) & 0xffff)

		reg_val = (((cs_time - 1) & 0xffff)

			   << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);

		reg_val |= (((cs_time - 1) & 0xffff)

			   << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);

		writel(reg_val, mdata->base + SPI_CFG0_REG);

	} else {

		reg_val |= (((sck_time - 1) & 0xff)

		reg_val = (((sck_time - 1) & 0xff)

			   << SPI_CFG0_SCK_HIGH_OFFSET);

		reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);

		reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);