Loading qcom/lagoon-sde.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,7 @@ "lut_clk"; clock-rate = <0 0 0 300000000 19200000 300000000>; clock-max-rate = <0 0 0 560000000 19200000 560000000>; qcom,dss-cx-ipeak = <&cx_ipeak_lm 4>; sde-vdd-supply = <&mdss_core_gdsc>; Loading qcom/lagoon.dtsi +16 −0 Original line number Diff line number Diff line Loading @@ -2885,6 +2885,11 @@ memory-region = <&pil_video_mem>; }; cx_ipeak_lm: cx_ipeak@1fed000 { compatible = "qcom,cx-ipeak-v2"; reg = <0x1fed000 0x9000>; }; qcom,npu@9800000 { compatible = "qcom,pil-tz-generic"; reg = <0x9800000 0x800000>; Loading Loading @@ -4325,5 +4330,16 @@ &usb_qmp_dp_phy { extcon = <&pm7250b_pdphy>; }; &msm_vidc0 { qcom,cx-ipeak-data = <&cx_ipeak_lm 5>; qcom,clock-freq-threshold = <460000000>; }; &msm_vidc1 { qcom,cx-ipeak-data = <&cx_ipeak_lm 5>; qcom,clock-freq-threshold = <380000000>; }; #include "lagoon-sde.dtsi" #include "lagoon-sde-pll.dtsi" Loading
qcom/lagoon-sde.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,7 @@ "lut_clk"; clock-rate = <0 0 0 300000000 19200000 300000000>; clock-max-rate = <0 0 0 560000000 19200000 560000000>; qcom,dss-cx-ipeak = <&cx_ipeak_lm 4>; sde-vdd-supply = <&mdss_core_gdsc>; Loading
qcom/lagoon.dtsi +16 −0 Original line number Diff line number Diff line Loading @@ -2885,6 +2885,11 @@ memory-region = <&pil_video_mem>; }; cx_ipeak_lm: cx_ipeak@1fed000 { compatible = "qcom,cx-ipeak-v2"; reg = <0x1fed000 0x9000>; }; qcom,npu@9800000 { compatible = "qcom,pil-tz-generic"; reg = <0x9800000 0x800000>; Loading Loading @@ -4325,5 +4330,16 @@ &usb_qmp_dp_phy { extcon = <&pm7250b_pdphy>; }; &msm_vidc0 { qcom,cx-ipeak-data = <&cx_ipeak_lm 5>; qcom,clock-freq-threshold = <460000000>; }; &msm_vidc1 { qcom,cx-ipeak-data = <&cx_ipeak_lm 5>; qcom,clock-freq-threshold = <380000000>; }; #include "lagoon-sde.dtsi" #include "lagoon-sde-pll.dtsi"