Merge "ARM: dts: msm: Include inline crypto as part of host controller" (d2fe4d02) · Commits · e / devices / android_kernel_fairphone_FP4

qcom/bengal.dtsi

+2 −28

Original line number	Diff line number	Diff line
		@@ -1515,32 +1515,6 @@
		status = "disabled";
		};

		ufs_ice: ufsice@4810000 {
		compatible = "qcom,ice";
		reg = <0x4810000 0x8000>;
		qcom,enable-ice-clk;
		clock-names = "ufs_core_clk", "bus_clk",
		"iface_clk", "ice_core_clk";
		clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
		<&gcc GCC_UFS_CLKREF_CLK>,
		<&gcc GCC_UFS_PHY_AHB_CLK>,
		<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
		vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
		qcom,msm-bus,name = "ufs_ice_noc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<MSM_BUS_MASTER_AMPSS_M0
		MSM_BUS_SLAVE_UFS_MEM_CFG 0 0>, /No vote/
		<MSM_BUS_MASTER_AMPSS_M0
		MSM_BUS_SLAVE_UFS_MEM_CFG 1000 0>;
		/* Max. bandwidth */
		qcom,bus-vector-names = "MIN",
		"MAX";
		qcom,instance-type = "ufs";
		};

		ufsphy_mem: ufsphy_mem@4807000 {
		reg = <0x4807000 0xdb8>; /* PHY regs */
		reg-names = "phy_mem";
		@@ -1560,11 +1534,11 @@

		ufshc_mem: ufshc@4804000 {
		compatible = "qcom,ufshc";
		reg = <0x4804000 0x3000>;
		reg = <0x4804000 0x3000>, <0x4810000 0x8000>;
		reg-names = "ufs_mem", "ufs_ice";
		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";
		ufs-qcom-crypto = <&ufs_ice>;

		lanes-per-direction = <1>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */

qcom/kona.dtsi

+4 −28

Original line number	Diff line number	Diff line
		@@ -2995,34 +2995,10 @@
		};
		};

		ufs_ice: ufsice@1d90000 {
		compatible = "qcom,ice";
		reg = <0x1d90000 0x8000>;
		qcom,enable-ice-clk;
		clock-names = "ufs_core_clk", "bus_clk",
		"iface_clk", "ice_core_clk";
		clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>,
		<&clock_gcc GCC_UFS_1X_CLKREF_EN>,
		<&clock_gcc GCC_UFS_PHY_AHB_CLK>,
		<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>;
		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
		vdd-hba-supply = <&ufs_phy_gdsc>;
		qcom,msm-bus,name = "ufs_ice_noc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<1 650 0 0>, /* No vote */
		<1 650 1000 0>; /* Max. bandwidth */
		qcom,bus-vector-names = "MIN",
		"MAX";
		qcom,instance-type = "ufs";
		};

		ufsphy_mem: ufsphy_mem@1d87000 {
		reg = <0x1d87000 0xe00>; /* PHY regs */
		reg-names = "phy_mem";
		reg = <0x1d87000 0xe00>, <0x1d90000 0x8000>; /* PHY regs */
		reg-names = "phy_mem", "ufs_ice";
		#phy-cells = <0>;
		ufs-qcom-crypto = <&ufs_ice>;

		lanes-per-direction = <2>;

		@@ -3036,11 +3012,11 @@

		ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x3000>;
		reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;
		reg-names = "ufs_mem", "ufs_ice";
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";
		ufs-qcom-crypto = <&ufs_ice>;

		lanes-per-direction = <2>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */

qcom/lito.dtsi

+6 −60

Original line number	Diff line number	Diff line
		@@ -1760,39 +1760,13 @@
		cell-index = <0>;
		};

		ufs_ice: ufsice@1d90000 {
		compatible = "qcom,ice";
		reg = <0x1d90000 0x8000>;
		qcom,enable-ice-clk;
		clock-names = "ufs_core_clk", "bus_clk",
		"iface_clk", "ice_core_clk";
		clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
		<&gcc GCC_UFS_1X_CLKREF_CLK>,
		<&gcc GCC_UFS_PHY_AHB_CLK>,
		<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
		vdd-hba-supply = <&ufs_phy_gdsc>;
		qcom,msm-bus,name = "ufs_ice_noc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<MSM_BUS_MASTER_AMPSS_M0
		MSM_BUS_SLAVE_UFS_CFG 0 0>, /* No vote */
		<MSM_BUS_MASTER_AMPSS_M0
		MSM_BUS_SLAVE_UFS_CFG 1000 0>;
		/* Max. bandwidth */
		qcom,bus-vector-names = "MIN",
		"MAX";
		qcom,instance-type = "ufs";
		};

		ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x3000>;
		reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;
		reg-names = "ufs_mem", "ufs_ice";
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";
		ufs-qcom-crypto = <&ufs_ice>;

		lanes-per-direction = <2>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */
		@@ -1900,41 +1874,14 @@
		status = "disabled";
		};

		sdcc1_ice: sdcc1ice@7c8000 {
		compatible = "qcom,ice";
		reg = <0x7c8000 0x8000>;
		qcom,enable-ice-clk;
		clock-names = "ice_core_clk_src", "ice_core_clk",
		"bus_clk", "iface_clk";
		clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK_SRC>,
		<&gcc GCC_SDCC1_ICE_CORE_CLK>,
		<&gcc GCC_SDCC1_AHB_CLK>,
		<&gcc GCC_SDCC1_APPS_CLK>;
		qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;
		qcom,msm-bus,name = "sdcc_ice_noc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<MSM_BUS_MASTER_AMPSS_M0
		MSM_BUS_SLAVE_UFS_MEM_CFG 0 0>,
		/* No vote */
		<MSM_BUS_MASTER_AMPSS_M0
		MSM_BUS_SLAVE_UFS_MEM_CFG 1000 0>;
		/* Max. bandwidth */
		qcom,bus-vector-names = "MIN",
		"MAX";
		qcom,instance-type = "sdcc";
		};

		sdhc_1: sdhci@7c4000 {
		compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";
		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>;
		reg-names = "hc_mem", "cqhci_mem";
		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7c8000 0x8000>;
		reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";

		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";
		sdhc-msm-crypto = <&sdcc1_ice>;

		qcom,bus-width = <8>;
		qcom,large-address-bus;
		@@ -2120,10 +2067,9 @@
		};

		ufsphy_mem: ufsphy_mem@1d87000 {
		reg = <0x1d87000 0xe00>; /* PHY regs */
		reg-names = "phy_mem";
		reg = <0x1d87000 0xe00>, <0x1d90000 0x8000>;
		reg-names = "phy_mem", "ufs_ice";
		#phy-cells = <0>;
		ufs-qcom-crypto = <&ufs_ice>;

		lanes-per-direction = <2>;
		qcom,rpmh-resource-name = "qphy.lvl";