Merge "drm/msm/sde: Add LTM interrupts into irq framework" (d2f35184) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+14 −0

Original line number	Diff line number	Diff line
		@@ -3573,11 +3573,15 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)

		if (IS_MSM8996_TARGET(hw_rev)) {
		sde_cfg->perf.min_prefill_lines = 21;
		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
		} else if (IS_MSM8998_TARGET(hw_rev)) {
		sde_cfg->has_wb_ubwc = true;
		sde_cfg->perf.min_prefill_lines = 25;
		sde_cfg->vbif_qos_nlvl = 4;
		sde_cfg->ts_prefill_rev = 1;
		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
		} else if (IS_SDM845_TARGET(hw_rev)) {
		sde_cfg->has_wb_ubwc = true;
		sde_cfg->has_cwb_support = true;
		@@ -3586,11 +3590,15 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
		sde_cfg->ts_prefill_rev = 2;
		sde_cfg->sui_misr_supported = true;
		sde_cfg->sui_block_xin_mask = 0x3F71;
		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
		} else if (IS_SDM670_TARGET(hw_rev)) {
		sde_cfg->has_wb_ubwc = true;
		sde_cfg->perf.min_prefill_lines = 24;
		sde_cfg->vbif_qos_nlvl = 8;
		sde_cfg->ts_prefill_rev = 2;
		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
		} else if (IS_SM8150_TARGET(hw_rev)) {
		sde_cfg->has_cwb_support = true;
		sde_cfg->has_wb_ubwc = true;
		@@ -3604,6 +3612,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
		sde_cfg->sui_misr_supported = true;
		sde_cfg->sui_block_xin_mask = 0x3F71;
		sde_cfg->has_3d_merge_reset = true;
		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
		} else if (IS_SDMSHRIKE_TARGET(hw_rev)) {
		sde_cfg->has_wb_ubwc = true;
		sde_cfg->perf.min_prefill_lines = 24;
		@@ -3611,6 +3621,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
		sde_cfg->ts_prefill_rev = 2;
		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
		sde_cfg->delay_prg_fetch_start = true;
		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
		} else if (IS_SM6150_TARGET(hw_rev)) {
		sde_cfg->has_cwb_support = true;
		sde_cfg->has_qsync = true;
		@@ -3622,6 +3634,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
		sde_cfg->sui_ns_allowed = true;
		sde_cfg->sui_misr_supported = true;
		sde_cfg->sui_block_xin_mask = 0x2EE1;
		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
		} else if (IS_KONA_TARGET(hw_rev)) {
		sde_cfg->has_cwb_support = true;
		sde_cfg->has_wb_ubwc = true;

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -118,6 +118,8 @@ enum sde_intr_enum {
		MDSS_INTR_INTF_4_INTR,
		MDSS_INTR_AD4_0_INTR,
		MDSS_INTR_AD4_1_INTR,
		MDSS_INTR_LTM_0_INTR,
		MDSS_INTR_LTM_1_INTR,
		MDSS_INTR_MAX
		};

drivers/gpu/drm/msm/sde/sde_hw_interrupts.c

+51 −0

Original line number	Diff line number	Diff line
		@@ -32,6 +32,11 @@
		#define MDP_INTF_TEAR_INTR_EN_OFF 0x0
		#define MDP_INTF_TEAR_INTR_STATUS_OFF 0x4
		#define MDP_INTF_TEAR_INTR_CLEAR_OFF 0x8
		#define MDP_LTM_0_OFF 0x7F000
		#define MDP_LTM_1_OFF 0x7F100
		#define MDP_LTM_INTR_EN_OFF 0x50
		#define MDP_LTM_INTR_STATUS_OFF 0x54
		#define MDP_LTM_INTR_CLEAR_OFF 0x58

		/**
		* WB interrupt status bit definitions
		@@ -189,6 +194,12 @@
		#define SDE_INTR_INTF_TEAR_TE_DETECTED BIT(3)
		#define SDE_INTR_INTF_TEAR_TEAR_DETECTED BIT(4)

		/**
		* LTM interrupt status bit definitions
		*/
		#define SDE_INTR_LTM_STATS_DONE BIT(0)
		#define SDE_INTR_LTM_STATS_WB_PB BIT(5)

		/**
		* struct sde_intr_reg - array of SDE register sets
		* @clr_off: offset to CLEAR reg
		@@ -532,6 +543,18 @@ static struct sde_irq_type sde_irq_intf2_te_map[] = {
		SDE_INTR_INTF_TEAR_TEAR_DETECTED, -1},
		};

		static struct sde_irq_type sde_irq_ltm_0_map[] = {

		{ SDE_IRQ_TYPE_LTM_STATS_DONE, DSPP_0, SDE_INTR_LTM_STATS_DONE, -1},
		{ SDE_IRQ_TYPE_LTM_STATS_WB_PB, DSPP_0, SDE_INTR_LTM_STATS_WB_PB, -1},
		};

		static struct sde_irq_type sde_irq_ltm_1_map[] = {

		{ SDE_IRQ_TYPE_LTM_STATS_DONE, DSPP_1, SDE_INTR_LTM_STATS_DONE, -1},
		{ SDE_IRQ_TYPE_LTM_STATS_WB_PB, DSPP_1, SDE_INTR_LTM_STATS_WB_PB, -1},
		};

		static int sde_hw_intr_irqidx_lookup(struct sde_hw_intr *intr,
		enum sde_intr_type intr_type, u32 instance_idx)
		{
		@@ -1154,6 +1177,22 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
		sde_irq->status_off = MDP_INTF_TEAR_INTF_2_IRQ_OFF +
		MDP_INTF_TEAR_INTR_STATUS_OFF;
		break;
		case MDSS_INTR_LTM_0_INTR:
		sde_irq->clr_off =
		MDP_LTM_0_OFF + MDP_LTM_INTR_CLEAR_OFF;
		sde_irq->en_off =
		MDP_LTM_0_OFF + MDP_LTM_INTR_EN_OFF;
		sde_irq->status_off =
		MDP_LTM_0_OFF + MDP_LTM_INTR_STATUS_OFF;
		break;
		case MDSS_INTR_LTM_1_INTR:
		sde_irq->clr_off =
		MDP_LTM_1_OFF + MDP_LTM_INTR_CLEAR_OFF;
		sde_irq->en_off =
		MDP_LTM_1_OFF + MDP_LTM_INTR_EN_OFF;
		sde_irq->status_off =
		MDP_LTM_1_OFF + MDP_LTM_INTR_STATUS_OFF;
		break;
		default:
		pr_err("wrong irq idx %d\n",
		sde_irq->sde_irq_idx);
		@@ -1220,6 +1259,12 @@ static inline u32 _get_irq_map_size(int idx)
		case MDSS_INTF_TEAR_2_INTR:
		ret = ARRAY_SIZE(sde_irq_intf2_te_map);
		break;
		case MDSS_INTR_LTM_0_INTR:
		ret = ARRAY_SIZE(sde_irq_ltm_0_map);
		break;
		case MDSS_INTR_LTM_1_INTR:
		ret = ARRAY_SIZE(sde_irq_ltm_1_map);
		break;
		default:
		pr_err("invalid idx:%d\n");
		}
		@@ -1268,6 +1313,12 @@ static inline struct sde_irq_type *_get_irq_map_addr(int idx)
		case MDSS_INTF_TEAR_2_INTR:
		ret = sde_irq_intf2_te_map;
		break;
		case MDSS_INTR_LTM_0_INTR:
		ret = sde_irq_ltm_0_map;
		break;
		case MDSS_INTR_LTM_1_INTR:
		ret = sde_irq_ltm_1_map;
		break;
		default:
		pr_err("invalid idx:%d\n");
		}

drivers/gpu/drm/msm/sde/sde_hw_interrupts.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -54,6 +54,8 @@
		* @SDE_IRQ_TYPE_INTF_TEAR_AUTO_REF: INTF Tear auto refresh
		* @SDE_IRQ_TYPE_INTF_TEAR_TEAR_CHECK: INTF Tear Tear check
		* @SDE_IRQ_TYPE_INTF_TEAR_TE_CHECK: INTF Tear TE detection
		* @SDE_IRQ_TYPE_LTM_STATS_DONE: LTM stats done interrupt
		* @SDE_IRQ_TYPE_LTM_STATS_WB_PB: LTM stats WB push back interrupt
		* @SDE_IRQ_TYPE_RESERVED: Reserved for expansion
		*/
		enum sde_intr_type {
		@@ -89,6 +91,8 @@ enum sde_intr_type {
		SDE_IRQ_TYPE_INTF_TEAR_AUTO_REF,
		SDE_IRQ_TYPE_INTF_TEAR_TEAR_CHECK,
		SDE_IRQ_TYPE_INTF_TEAR_TE_CHECK,
		SDE_IRQ_TYPE_LTM_STATS_DONE,
		SDE_IRQ_TYPE_LTM_STATS_WB_PB,
		SDE_IRQ_TYPE_RESERVED,
		};