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Commit d2c2ba69 authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge branches 'acpi-soc', 'acpi-battery', 'acpi-video', 'acpi-cppc' and 'acpi-apei' 

* acpi-soc:
  ACPI / LPSS: enable hard LLP for DMA
  ACPI / APD: Add clock frequency for future AMD I2C controller

* acpi-battery:
  ACPI / battery: If _BIX fails, retry with _BIF

* acpi-video:
  ACPI / video: Add force_native quirk for HP Pavilion dv6
  ACPI / video: Add force_native quirk for Dell XPS 17 L702X
  ACPI / video: Move ACPI_VIDEO_NOTIFY_* defines to acpi/video.h

* acpi-cppc:
  ACPI / CPPC: set an error code on probe error path

* acpi-apei:
  ACPI / APEI / ARM64: APEI initial support for ARM64
  ACPI / APEI: Fix NMI notification handling
parents 3e16164e d132d6d5 2d09af4a 6276e53f 50163475 9f9a35a7

arch/arm64/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ config ARM64 
	select GENERIC_TIME_VSYSCALL

	select HANDLE_DOMAIN_IRQ

	select HARDIRQS_SW_RESEND

	select HAVE_ACPI_APEI if (ACPI && EFI)

	select HAVE_ALIGNED_STRUCT_PAGE if SLUB

	select HAVE_ARCH_AUDITSYSCALL

	select HAVE_ARCH_BITREVERSE

arch/arm64/include/asm/acpi.h

+22 −1
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 


#include <asm/cputype.h>

#include <asm/smp_plat.h>

#include <asm/tlbflush.h>



/* Macros for consistency checks of the GICC subtable of MADT */

#define ACPI_MADT_GICC_LENGTH	\
@@ -114,8 +115,28 @@ static inline const char *acpi_get_enable_method(int cpu) 
}



#ifdef	CONFIG_ACPI_APEI

/*

 * acpi_disable_cmcff is used in drivers/acpi/apei/hest.c for disabling

 * IA-32 Architecture Corrected Machine Check (CMC) Firmware-First mode

 * with a kernel command line parameter "acpi=nocmcoff". But we don't

 * have this IA-32 specific feature on ARM64, this definition is only

 * for compatibility.

 */

#define acpi_disable_cmcff 1

pgprot_t arch_apei_get_mem_attribute(phys_addr_t addr);

#endif



/*

 * Despite its name, this function must still broadcast the TLB

 * invalidation in order to ensure other CPUs don't end up with junk

 * entries as a result of speculation. Unusually, its also called in

 * IRQ context (ghes_iounmap_irq) so if we ever need to use IPIs for

 * TLB broadcasting, then we're in trouble here.

 */

static inline void arch_apei_flush_tlb_one(unsigned long addr)

{

	flush_tlb_kernel_range(addr, addr + PAGE_SIZE);

}

#endif /* CONFIG_ACPI_APEI */



#ifdef CONFIG_ACPI_NUMA

int arm64_acpi_numa_init(void);

arch/x86/kernel/acpi/apei.c

+0 −3
Original line number Diff line number Diff line
@@ -24,9 +24,6 @@ int arch_apei_enable_cmcff(struct acpi_hest_header *hest_hdr, void *data) 
	struct acpi_hest_ia_corrected *cmc;

	struct acpi_hest_ia_error_bank *mc_bank;



	if (hest_hdr->type != ACPI_HEST_TYPE_IA32_CORRECTED_CHECK)

		return 0;



	cmc = (struct acpi_hest_ia_corrected *)hest_hdr;

	if (!cmc->enabled)

		return 0;

drivers/acpi/acpi_apd.c

+6 −1
Original line number Diff line number Diff line
@@ -77,6 +77,11 @@ static const struct apd_device_desc cz_i2c_desc = { 
	.fixed_clk_rate = 133000000,

};



static const struct apd_device_desc wt_i2c_desc = {

	.setup = acpi_apd_setup,

	.fixed_clk_rate = 150000000,

};



static struct property_entry uart_properties[] = {

	PROPERTY_ENTRY_U32("reg-io-width", 4),

	PROPERTY_ENTRY_U32("reg-shift", 2),
@@ -156,7 +161,7 @@ static const struct acpi_device_id acpi_apd_device_ids[] = { 
	/* Generic apd devices */

#ifdef CONFIG_X86_AMD_PLATFORM_DEVICE

	{ "AMD0010", APD_ADDR(cz_i2c_desc) },

	{ "AMDI0010", APD_ADDR(cz_i2c_desc) },

	{ "AMDI0010", APD_ADDR(wt_i2c_desc) },

	{ "AMD0020", APD_ADDR(cz_uart_desc) },

	{ "AMDI0020", APD_ADDR(cz_uart_desc) },

	{ "AMD0030", },

drivers/acpi/acpi_lpss.c

+5 −3
Original line number Diff line number Diff line
@@ -718,13 +718,14 @@ static int acpi_lpss_resume_early(struct device *dev) 
#define LPSS_GPIODEF0_DMA1_D3		BIT(2)

#define LPSS_GPIODEF0_DMA2_D3		BIT(3)

#define LPSS_GPIODEF0_DMA_D3_MASK	GENMASK(3, 2)

#define LPSS_GPIODEF0_DMA_LLP		BIT(13)



static DEFINE_MUTEX(lpss_iosf_mutex);



static void lpss_iosf_enter_d3_state(void)

{

	u32 value1 = 0;

	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK;

	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;

	u32 value2 = LPSS_PMCSR_D3hot;

	u32 mask2 = LPSS_PMCSR_Dx_MASK;

	/*
@@ -768,8 +769,9 @@ static void lpss_iosf_enter_d3_state(void) 


static void lpss_iosf_exit_d3_state(void)

{

	u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3;

	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK;

	u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |

		     LPSS_GPIODEF0_DMA_LLP;

	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;

	u32 value2 = LPSS_PMCSR_D0;

	u32 mask2 = LPSS_PMCSR_Dx_MASK;