Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d1f1f98c authored by David S. Miller's avatar David S. Miller
Browse files

sparc64: Set %l4 properly on trap return after handling signals.



If we did some signal processing, we have to reload the pt_regs
tstate register because it's value may have changed.

In doing so we also have to extract the %pil value contained in there
anre load that into %l4.

This value is at bit 20 and thus needs to be shifted down before we
later write it into the %pil register.

Most of the time this is harmless as we are returning to userspace
and the %pil is zero for that case.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b3e1eb8e
Loading
Loading
Loading
Loading
+2 −1
Original line number Diff line number Diff line
@@ -84,8 +84,9 @@ __handle_signal:
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		ba,pt			%xcc, __handle_preemption_continue
		andn			%l1, %l4, %l1
		ba,pt			%xcc, __handle_preemption_continue
		 srl			%l4, 20, %l4

		/* When returning from a NMI (%pil==15) interrupt we want to
		 * avoid running softirqs, doing IRQ tracing, preempting, etc.