Staging: rt2870: prepare for rt{28,30}70/*.[ch] merge (d1e4861a) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/staging/rt2870/2870_main_dev.c

+89 −2

Original line number	Diff line number	Diff line
		@@ -234,7 +234,12 @@ INT MlmeThread(
		*/
		DBGPRINT(RT_DEBUG_TRACE,( "<---%s\n",__func__));

		#ifndef RT30xx
		pObj->MLMEThr_task = NULL;
		#endif
		#ifdef RT30xx
		pObj->MLMEThr_pid = NULL;
		#endif

		complete_and_exit (&pAd->mlmeComplete, 0);
		return 0;
		@@ -342,7 +347,12 @@ INT RTUSBCmdThread(
		*/
		DBGPRINT(RT_DEBUG_TRACE,( "<---RTUSBCmdThread\n"));

		#ifndef RT30xx
		pObj->RTUSBCmdThr_task = NULL;
		#endif
		#ifdef RT30xx
		pObj->RTUSBCmdThr_pid = NULL;
		#endif

		complete_and_exit (&pAd->CmdQComplete, 0);
		return 0;
		@@ -436,8 +446,12 @@ INT TimerQThread(
		*/
		DBGPRINT(RT_DEBUG_TRACE,( "<---%s\n",__func__));

		#ifndef RT30xx
		pObj->TimerQThr_task = NULL;

		#endif
		#ifdef RT30xx
		pObj->TimerQThr_pid = NULL;
		#endif
		complete_and_exit(&pAd->TimerQComplete, 0);
		return 0;

		@@ -605,6 +619,7 @@ VOID RT2870_WatchDog(IN RTMP_ADAPTER *pAd)
		RTMP_IO_WRITE32(pAd, PBF_CFG, 0xf40006);
		}

		//PS packets use HCCA queue when dequeue from PS unicast queue (WiFi WPA2 MA9_DT1 for Marvell B STA)
		idx = 0;
		if ((MACValue & 0xff00) !=0 )
		{
		@@ -618,7 +633,6 @@ VOID RT2870_WatchDog(IN RTMP_ADAPTER *pAd)
		RTMP_IO_WRITE32(pAd, PBF_CFG, 0xf40006);
		}


		if (pAd->watchDogRxOverFlowCnt >= 2)
		{
		DBGPRINT(RT_DEBUG_TRACE, ("Maybe the Rx Bulk-In hanged! Cancel the pending Rx bulks request!\n"));
		@@ -868,6 +882,7 @@ VOID RT28xxThreadTerminate(
		RTUSBCancelPendingIRPs(pAd);

		// Terminate Threads
		#ifndef RT30xx
		BUG_ON(pObj->TimerQThr_task == NULL);
		CHECK_PID_LEGALITY(task_pid(pObj->TimerQThr_task))
		{
		@@ -909,7 +924,72 @@ VOID RT28xxThreadTerminate(
		kthread_stop(pObj->RTUSBCmdThr_task);
		pObj->RTUSBCmdThr_task = NULL;
		}
		#endif
		#ifdef RT30xx
		if (pObj->MLMEThr_pid)
		{
		printk("Terminate the MLMEThr_pid=%d!\n", pid_nr(pObj->MLMEThr_pid));
		mb();
		pAd->mlme_kill = 1;
		//RT28XX_MLME_HANDLER(pAd);
		mb();
		ret = kill_pid(pObj->MLMEThr_pid, SIGTERM, 1);
		if (ret)
		{
		printk (KERN_WARNING "%s: unable to Mlme thread, pid=%d, ret=%d!\n",
		pAd->net_dev->name, pid_nr(pObj->MLMEThr_pid), ret);
		}
		else
		{
		//wait_for_completion (&pAd->notify);
		wait_for_completion (&pAd->mlmeComplete);
		pObj->MLMEThr_pid = NULL;
		}
		}

		if (pObj->RTUSBCmdThr_pid >= 0)
		{
		printk("Terminate the RTUSBCmdThr_pid=%d!\n", pid_nr(pObj->RTUSBCmdThr_pid));
		mb();
		NdisAcquireSpinLock(&pAd->CmdQLock);
		pAd->CmdQ.CmdQState = RT2870_THREAD_STOPED;
		NdisReleaseSpinLock(&pAd->CmdQLock);
		mb();
		//RTUSBCMDUp(pAd);
		ret = kill_pid(pObj->RTUSBCmdThr_pid, SIGTERM, 1);
		if (ret)
		{
		printk(KERN_WARNING "%s: unable to RTUSBCmd thread, pid=%d, ret=%d!\n",
		pAd->net_dev->name, pid_nr(pObj->RTUSBCmdThr_pid), ret);
		}
		else
		{
		//wait_for_completion (&pAd->notify);
		wait_for_completion (&pAd->CmdQComplete);
		pObj->RTUSBCmdThr_pid = NULL;
		}
		}
		if (pObj->TimerQThr_pid >= 0)
		{
		POS_COOKIE pObj = (POS_COOKIE)pAd->OS_Cookie;
		printk("Terminate the TimerQThr_pid=%d!\n", pid_nr(pObj->TimerQThr_pid));
		mb();
		pAd->TimerFunc_kill = 1;
		mb();
		ret = kill_pid(pObj->TimerQThr_pid, SIGTERM, 1);
		if (ret)
		{
		printk(KERN_WARNING "%s: unable to stop TimerQThread, pid=%d, ret=%d!\n",
		pAd->net_dev->name, pid_nr(pObj->TimerQThr_pid), ret);
		}
		else
		{
		printk("wait_for_completion TimerQThr\n");
		wait_for_completion(&pAd->TimerQComplete);
		pObj->TimerQThr_pid = NULL;
		}
		}
		#endif

		// Kill tasklets
		pAd->mlme_kill = 0;
		@@ -964,7 +1044,12 @@ BOOLEAN RT28XXChipsetCheck(
		if (dev_p->descriptor.idVendor == rtusb_usb_id[i].idVendor &&
		dev_p->descriptor.idProduct == rtusb_usb_id[i].idProduct)
		{
		#ifndef RT30xx
		printk(KERN_DEBUG "rt2870: idVendor = 0x%x, idProduct = 0x%x\n",
		#endif
		#ifdef RT30xx
		printk("rt2870: idVendor = 0x%x, idProduct = 0x%x\n",
		#endif
		dev_p->descriptor.idVendor, dev_p->descriptor.idProduct);
		break;
		}
		@@ -1262,6 +1347,8 @@ VOID RT28xx_UpdateBeaconToAsic(
		}

		pBeaconSync->BeaconBitMap \|= (1 << bcn_idx);

		// For AP interface, set the DtimBitOn so that we can send Bcast/Mcast frame out after this beacon frame.
		}

		}

drivers/staging/rt2870/chlist.h

+5 −0

Original line number	Diff line number	Diff line
		@@ -524,7 +524,12 @@ static CH_REGION ChRegion[] =
		JAP,
		{
		{ 1, 14, 20, BOTH, FALSE}, // 2.4 G, ch 1~14
		#ifndef RT30xx
		{ 36, 4, 23, IDOR, FALSE}, // 5G, ch 36~48
		#endif
		#ifdef RT30xx
		{ 34, 4, 23, IDOR, FALSE}, // 5G, ch 34~46
		#endif
		{ 0}, // end
		}
		},

drivers/staging/rt2870/oid.h

+41 −0

Original line number	Diff line number	Diff line
		@@ -534,8 +534,10 @@ typedef enum _NDIS_802_11_WEP_STATUS
		Ndis802_11Encryption3KeyAbsent,
		Ndis802_11Encryption4Enabled, // TKIP or AES mix
		Ndis802_11Encryption4KeyAbsent,
		#ifndef RT30xx
		Ndis802_11GroupWEP40Enabled,
		Ndis802_11GroupWEP104Enabled,
		#endif
		} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
		NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;

		@@ -630,11 +632,17 @@ typedef struct _NDIS_802_11_CAPABILITY
		#define SIOCIWFIRSTPRIV SIOCDEVPRIVATE
		#endif

		#ifdef RT30xx
		#define RT_PRIV_IOCTL_EXT (SIOCIWFIRSTPRIV + 0x01) // Sync. with AP for wsc upnp daemon
		#endif
		#define RTPRIV_IOCTL_SET (SIOCIWFIRSTPRIV + 0x02)

		#ifdef DBG
		#define RTPRIV_IOCTL_BBP (SIOCIWFIRSTPRIV + 0x03)
		#define RTPRIV_IOCTL_MAC (SIOCIWFIRSTPRIV + 0x05)
		#ifdef RT30xx
		#define RTPRIV_IOCTL_RF (SIOCIWFIRSTPRIV + 0x13)
		#endif
		#define RTPRIV_IOCTL_E2P (SIOCIWFIRSTPRIV + 0x07)
		#endif

		@@ -658,7 +666,9 @@ enum {
		RAIO_OFF = 10,
		RAIO_ON = 11,
		SHOW_CFG_VALUE = 20,
		#ifndef RT30xx
		SHOW_ADHOC_ENTRY_INFO = 21,
		#endif
		};

		#define OID_802_11_BUILD_CHANNEL_EX 0x0714
		@@ -666,11 +676,42 @@ enum {
		#define OID_802_11_GET_COUNTRY_CODE 0x0716
		#define OID_802_11_GET_CHANNEL_GEOGRAPHY 0x0717

		#ifdef RT30xx
		#define RT_OID_WSC_SET_PASSPHRASE 0x0740 // passphrase for wpa(2)-psk
		#define RT_OID_WSC_DRIVER_AUTO_CONNECT 0x0741
		#define RT_OID_WSC_QUERY_DEFAULT_PROFILE 0x0742
		#define RT_OID_WSC_SET_CONN_BY_PROFILE_INDEX 0x0743
		#define RT_OID_WSC_SET_ACTION 0x0744
		#define RT_OID_WSC_SET_SSID 0x0745
		#define RT_OID_WSC_SET_PIN_CODE 0x0746
		#define RT_OID_WSC_SET_MODE 0x0747 // PIN or PBC
		#define RT_OID_WSC_SET_CONF_MODE 0x0748 // Enrollee or Registrar
		#define RT_OID_WSC_SET_PROFILE 0x0749

		#define RT_OID_802_11_WSC_QUERY_PROFILE 0x0750
		// for consistency with RT61
		#define RT_OID_WSC_QUERY_STATUS 0x0751
		#define RT_OID_WSC_PIN_CODE 0x0752
		#define RT_OID_WSC_UUID 0x0753
		#define RT_OID_WSC_SET_SELECTED_REGISTRAR 0x0754
		#define RT_OID_WSC_EAPMSG 0x0755
		#define RT_OID_WSC_MANUFACTURER 0x0756
		#define RT_OID_WSC_MODEL_NAME 0x0757
		#define RT_OID_WSC_MODEL_NO 0x0758
		#define RT_OID_WSC_SERIAL_NO 0x0759
		#define RT_OID_WSC_MAC_ADDRESS 0x0760
		#endif

		#ifdef LLTD_SUPPORT
		// for consistency with RT61
		#define RT_OID_GET_PHY_MODE 0x761
		#endif // LLTD_SUPPORT //

		#ifdef RT30xx
		// New for MeetingHouse Api support
		#define OID_MH_802_1X_SUPPORTED 0xFFEDC100
		#endif

		// MIMO Tx parameter, ShortGI, MCS, STBC, etc. these are fields in TXWI. Don't change this definition!!!
		typedef union _HTTRANSMIT_SETTING {
		struct {

drivers/staging/rt2870/rt2870.h

+137 −1

Original line number	Diff line number	Diff line
		@@ -46,7 +46,9 @@
		#define MAX_TXBULK_SIZE (LOCAL_TXBUF_SIZE*BULKAGGRE_ZISE)
		#define MAX_RXBULK_SIZE (LOCAL_TXBUF_SIZE*RXBULKAGGRE_ZISE)
		#define MAX_MLME_HANDLER_MEMORY 20
		#ifndef RT30xx
		#define RETRY_LIMIT 10
		#endif
		#define BUFFER_SIZE 2400 //2048
		#define TX_RING 0xa
		#define PRIO_RING 0xc
		@@ -62,6 +64,9 @@
		#define fRTUSB_BULK_OUT_DATA_NORMAL_2 0x00020000
		#define fRTUSB_BULK_OUT_DATA_NORMAL_3 0x00040000
		#define fRTUSB_BULK_OUT_DATA_NORMAL_4 0x00080000
		#ifdef RT30xx
		#define fRTUSB_BULK_OUT_DATA_NORMAL_5 0x00100000
		#endif

		#define fRTUSB_BULK_OUT_PSPOLL 0x00000020
		#define fRTUSB_BULK_OUT_DATA_FRAG 0x00000040
		@@ -69,6 +74,7 @@
		#define fRTUSB_BULK_OUT_DATA_FRAG_3 0x00000100
		#define fRTUSB_BULK_OUT_DATA_FRAG_4 0x00000200

		#ifndef RT30xx
		#define RT2870_USB_DEVICES \
		{ \
		{USB_DEVICE(0x148F,0x2770)}, /* Ralink */ \
		@@ -134,6 +140,84 @@
		{USB_DEVICE(0x7392,0x7717)}, /* Edimax */ \
		{ }/* Terminating entry */ \
		}
		#endif
		#ifdef RT30xx
		#define RT2870_USB_DEVICES \
		{ \
		{USB_DEVICE(0x148F,0x2770)}, /* Ralink */ \
		{USB_DEVICE(0x148F,0x2870)}, /* Ralink */ \
		{USB_DEVICE(0x148F,0x3070)}, /* Ralink 3070 */ \
		{USB_DEVICE(0x148F,0x3071)}, /* Ralink 3071 */ \
		{USB_DEVICE(0x148F,0x3072)}, /* Ralink 3072 */ \
		{USB_DEVICE(0x0B05,0x1731)}, /* Asus */ \
		{USB_DEVICE(0x0B05,0x1732)}, /* Asus */ \
		{USB_DEVICE(0x0B05,0x1742)}, /* Asus */ \
		{USB_DEVICE(0x0DF6,0x0017)}, /* Sitecom */ \
		{USB_DEVICE(0x0DF6,0x002B)}, /* Sitecom */ \
		{USB_DEVICE(0x0DF6,0x002C)}, /* Sitecom */ \
		{USB_DEVICE(0x0DF6,0x003E)}, /* Sitecom 3070 */ \
		{USB_DEVICE(0x0DF6,0x002D)}, /* Sitecom */ \
		{USB_DEVICE(0x0DF6,0x0039)}, /* Sitecom 2770 */ \
		{USB_DEVICE(0x14B2,0x3C06)}, /* Conceptronic */ \
		{USB_DEVICE(0x14B2,0x3C28)}, /* Conceptronic */ \
		{USB_DEVICE(0x2019,0xED06)}, /* Planex Communications, Inc. */ \
		{USB_DEVICE(0x2019,0xAB25)}, /* Planex Communications, Inc. RT3070 */ \
		{USB_DEVICE(0x07D1,0x3C09)}, /* D-Link */ \
		{USB_DEVICE(0x07D1,0x3C11)}, /* D-Link */ \
		{USB_DEVICE(0x2001,0x3C09)}, /* D-Link */ \
		{USB_DEVICE(0x2001,0x3C0A)}, /* D-Link 3072*/ \
		{USB_DEVICE(0x14B2,0x3C07)}, /* AL */ \
		{USB_DEVICE(0x14B2,0x3C12)}, /* AL 3070 */ \
		{USB_DEVICE(0x050D,0x8053)}, /* Belkin */ \
		{USB_DEVICE(0x14B2,0x3C23)}, /* Airlink */ \
		{USB_DEVICE(0x14B2,0x3C27)}, /* Airlink */ \
		{USB_DEVICE(0x07AA,0x002F)}, /* Corega */ \
		{USB_DEVICE(0x07AA,0x003C)}, /* Corega */ \
		{USB_DEVICE(0x07AA,0x003F)}, /* Corega */ \
		{USB_DEVICE(0x18C5,0x0012)}, /* Corega 3070 */ \
		{USB_DEVICE(0x1044,0x800B)}, /* Gigabyte */ \
		{USB_DEVICE(0x1044,0x800D)}, /* Gigabyte GN-WB32L 3070 */ \
		{USB_DEVICE(0x15A9,0x0006)}, /* Sparklan */ \
		{USB_DEVICE(0x083A,0xB522)}, /* SMC */ \
		{USB_DEVICE(0x083A,0xA618)}, /* SMC */ \
		{USB_DEVICE(0x083A,0x8522)}, /* Arcadyan */ \
		{USB_DEVICE(0x083A,0x7512)}, /* Arcadyan 2770 */ \
		{USB_DEVICE(0x083A,0x7522)}, /* Arcadyan */ \
		{USB_DEVICE(0x083A,0x7511)}, /* Arcadyan 3070 */ \
		{USB_DEVICE(0x0CDE,0x0022)}, /* ZCOM */ \
		{USB_DEVICE(0x0586,0x3416)}, /* Zyxel */ \
		{USB_DEVICE(0x0CDE,0x0025)}, /* Zyxel */ \
		{USB_DEVICE(0x1740,0x9701)}, /* EnGenius */ \
		{USB_DEVICE(0x1740,0x9702)}, /* EnGenius */ \
		{USB_DEVICE(0x1740,0x9703)}, /* EnGenius 3070 */ \
		{USB_DEVICE(0x0471,0x200f)}, /* Philips */ \
		{USB_DEVICE(0x14B2,0x3C25)}, /* Draytek */ \
		{USB_DEVICE(0x13D3,0x3247)}, /* AzureWave */ \
		{USB_DEVICE(0x13D3,0x3273)}, /* AzureWave 3070*/ \
		{USB_DEVICE(0x083A,0x6618)}, /* Accton */ \
		{USB_DEVICE(0x15c5,0x0008)}, /* Amit */ \
		{USB_DEVICE(0x0E66,0x0001)}, /* Hawking */ \
		{USB_DEVICE(0x0E66,0x0003)}, /* Hawking */ \
		{USB_DEVICE(0x129B,0x1828)}, /* Siemens */ \
		{USB_DEVICE(0x157E,0x300E)}, /* U-Media */ \
		{USB_DEVICE(0x050d,0x805c)}, \
		{USB_DEVICE(0x1482,0x3C09)}, /* Abocom*/ \
		{USB_DEVICE(0x14B2,0x3C09)}, /* Alpha */ \
		{USB_DEVICE(0x04E8,0x2018)}, /* samsung */ \
		{USB_DEVICE(0x07B8,0x3070)}, /* AboCom 3070 */ \
		{USB_DEVICE(0x07B8,0x3071)}, /* AboCom 3071 */ \
		{USB_DEVICE(0x07B8,0x3072)}, /* Abocom 3072 */ \
		{USB_DEVICE(0x7392,0x7711)}, /* Edimax 3070 */ \
		{USB_DEVICE(0x5A57,0x0280)}, /* Zinwell */ \
		{USB_DEVICE(0x5A57,0x0282)}, /* Zinwell */ \
		{USB_DEVICE(0x1A32,0x0304)}, /* Quanta 3070 */ \
		{USB_DEVICE(0x0789,0x0162)}, /* Logitec 2870 */ \
		{USB_DEVICE(0x0789,0x0163)}, /* Logitec 2870 */ \
		{USB_DEVICE(0x0789,0x0164)}, /* Logitec 2870 */ \
		{USB_DEVICE(0x1EDA,0x2310)}, /* AirTies 3070 */ \
		{ }/* Terminating entry */ \
		}
		#endif

		#define FREE_HTTX_RING(_p, _b, _t) \
		{ \
		@@ -200,6 +284,23 @@ typedef struct _MGMT_STRUC {


		/* ----------------- EEPROM Related MACRO ----------------- */
		#ifdef RT30xx
		#define RT28xx_EEPROM_READ16(pAd, offset, var) \
		do { \
		RTUSBReadEEPROM(pAd, offset, (PUCHAR)&(var), 2); \
		if(!pAd->bUseEfuse) \
		var = le2cpu16(var); \
		}while(0)

		#define RT28xx_EEPROM_WRITE16(pAd, offset, var) \
		do{ \
		USHORT _tmpVar=var; \
		if(!pAd->bUseEfuse) \
		_tmpVar = cpu2le16(var); \
		RTUSBWriteEEPROM(pAd, offset, (PUCHAR)&(_tmpVar), 2); \
		}while(0)
		#endif // RT30xx //
		#ifndef RT30xx
		#define RT28xx_EEPROM_READ16(pAd, offset, var) \
		do { \
		RTUSBReadEEPROM(pAd, offset, (PUCHAR)&(var), 2); \
		@@ -212,6 +313,7 @@ typedef struct _MGMT_STRUC {
		_tmpVar = cpu2le16(var); \
		RTUSBWriteEEPROM(pAd, offset, (PUCHAR)&(_tmpVar), 2); \
		}while(0)
		#endif // RT30xx //

		/* ----------------- TASK/THREAD Related MACRO ----------------- */
		#define RT28XX_TASK_THREAD_INIT(pAd, Status) \
		@@ -327,6 +429,14 @@ extern UCHAR EpToQueue[6];
		RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_SET_CLIENT_MAC_ENTRY, \
		pEntry, sizeof(MAC_TABLE_ENTRY));

		#ifdef RT30xx
		// add by johnli, fix "in_interrupt" error when call "MacTableDeleteEntry" in Rx tasklet
		// Set MAC register value according operation mode
		#define RT28XX_UPDATE_PROTECT(pAd) \
		RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_UPDATE_PROTECT, NULL, 0);
		// end johnli
		#endif

		// remove Pair-wise key material from ASIC
		// yet implement
		#define RT28XX_STA_ENTRY_KEY_DEL(pAd, BssIdx, Wcid)
		@@ -414,8 +524,10 @@ extern UCHAR EpToQueue[6];

		#define RT28xx_CHIP_NAME "RT2870"
		#define USB_CYC_CFG 0x02a4
		#ifndef RT30xx
		#define STATUS_SUCCESS 0x00
		#define STATUS_UNSUCCESSFUL 0x01
		#endif
		#define NT_SUCCESS(status) (((status) > 0) ? (1):(0))
		#define InterlockedIncrement atomic_inc
		#define NdisInterlockedIncrement atomic_inc
		@@ -440,7 +552,9 @@ extern UCHAR EpToQueue[6];
		//#undef MlmeAllocateMemory
		//#undef MlmeFreeMemory

		#ifndef RT30xx
		typedef int NTSTATUS;
		#endif
		typedef struct usb_device * PUSB_DEV;

		/* MACRO for linux usb */
		@@ -468,7 +582,7 @@ VOID RTUSBBulkOutRTSFrameComplete(purbb_t pUrb, struct pt_regs *pt_regs);
		VOID RTUSBBulkOutPsPollComplete(purbb_t pUrb, struct pt_regs *pt_regs);
		VOID RTUSBBulkRxComplete(purbb_t pUrb, struct pt_regs *pt_regs);


		#ifndef RT30xx
		#define RTUSBMlmeUp(pAd) \
		{ \
		POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie; \
		@@ -484,7 +598,22 @@ VOID RTUSBBulkRxComplete(purbb_t pUrb, struct pt_regs *pt_regs);
		CHECK_PID_LEGALITY(task_pid(pObj->RTUSBCmdThr_task)) \
		up(&(pAd->RTUSBCmd_semaphore)); \
		}
		#endif
		#ifdef RT30xx
		#define RTUSBMlmeUp(pAd) \
		{ \
		POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie; \
		if(pObj->MLMEThr_pid>0) \
		up(&(pAd->mlme_semaphore)); \
		}

		#define RTUSBCMDUp(pAd) \
		{ \
		POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie; \
		if(pObj->RTUSBCmdThr_pid>0) \
		up(&(pAd->RTUSBCmd_semaphore)); \
		}
		#endif

		static inline NDIS_STATUS RTMPAllocateMemory(
		OUT PVOID *ptr,
		@@ -526,7 +655,9 @@ typedef struct _RT_SET_ASIC_WCID {
		ULONG WCID; // mechanism for rekeying: 0:disable, 1: time-based, 2: packet-based
		ULONG SetTid; // time-based: seconds, packet-based: kilo-packets
		ULONG DeleteTid; // time-based: seconds, packet-based: kilo-packets
		#ifndef RT30xx
		UCHAR Addr[MAC_ADDR_LEN]; // avoid in interrupt when write key
		#endif
		} RT_SET_ASIC_WCID,*PRT_SET_ASIC_WCID;

		typedef struct _RT_SET_ASIC_WCID_ATTRI {
		@@ -628,6 +759,11 @@ typedef struct _CMDHandler_TLV {
		#define CMDTHREAD_802_11_SET_PREAMBLE 0x0D790101 // cmd
		#define CMDTHREAD_802_11_COUNTER_MEASURE 0x0D790102 // cmd

		#ifdef RT30xx
		// add by johnli, fix "in_interrupt" error when call "MacTableDeleteEntry" in Rx tasklet
		#define CMDTHREAD_UPDATE_PROTECT 0x0D790103 // cmd
		// end johnli
		#endif

		#define WPA1AKMBIT 0x01
		#define WPA2AKMBIT 0x02

drivers/staging/rt2870/rt28xx.h

+57 −0

Original line number	Diff line number	Diff line
		@@ -47,6 +47,15 @@
		#define PCI_EECTRL 0x0004
		#define PCI_MCUCTRL 0x0008

		#ifdef RT30xx
		#define OPT_14 0x114

		typedef int NTSTATUS;
		#define RETRY_LIMIT 10
		#define STATUS_SUCCESS 0x00
		#define STATUS_UNSUCCESSFUL 0x01
		#endif

		//
		// SCH/DMA registers - base address 0x0200
		//
		@@ -282,6 +291,36 @@ typedef union _USB_DMA_CFG_STRUC {
		#define PBF_DBG 0x043c
		#define PBF_CAP_CTRL 0x0440

		#ifdef RT30xx
		// eFuse registers
		#define EFUSE_CTRL 0x0580
		#define EFUSE_DATA0 0x0590
		#define EFUSE_DATA1 0x0594
		#define EFUSE_DATA2 0x0598
		#define EFUSE_DATA3 0x059c
		#define EFUSE_USAGE_MAP_START 0x2d0
		#define EFUSE_USAGE_MAP_END 0x2fc
		#define EFUSE_TAG 0x2fe
		#define EFUSE_USAGE_MAP_SIZE 45

		typedef union _EFUSE_CTRL_STRUC {
		struct {
		UINT32 EFSROM_AOUT:6;
		UINT32 EFSROM_MODE:2;
		UINT32 EFSROM_LDO_OFF_TIME:6;
		UINT32 EFSROM_LDO_ON_TIME:2;
		UINT32 EFSROM_AIN:10;
		UINT32 RESERVED:4;
		UINT32 EFSROM_KICK:1;
		UINT32 SEL_EFUSE:1;
		} field;
		UINT32 word;
		} EFUSE_CTRL_STRUC, *PEFUSE_CTRL_STRUC;

		#define LDO_CFG0 0x05d4
		#define GPIO_SWITCH 0x05dc
		#endif /* RT30xx */

		//
		// 4 MAC registers
		//
		@@ -1093,6 +1132,9 @@ typedef struct _HW_WCID_ENTRY { // 8-byte per entry
		#define BBP_R22 22
		#define BBP_R24 24
		#define BBP_R25 25
		#ifdef RT30xx
		#define BBP_R31 31
		#endif
		#define BBP_R49 49 //TSSI
		#define BBP_R50 50
		#define BBP_R51 51
		@@ -1110,6 +1152,10 @@ typedef struct _HW_WCID_ENTRY { // 8-byte per entry
		#define BBP_R73 73
		#define BBP_R75 75
		#define BBP_R77 77
		#ifdef RT30xx
		#define BBP_R79 79
		#define BBP_R80 80
		#endif
		#define BBP_R81 81
		#define BBP_R82 82
		#define BBP_R83 83
		@@ -1131,6 +1177,9 @@ typedef struct _HW_WCID_ENTRY { // 8-byte per entry
		#define BBP_R121 121
		#define BBP_R122 122
		#define BBP_R123 123
		#ifdef RT30xx
		#define BBP_R138 138 // add by johnli, RF power sequence setup, ADC dynamic on/off control
		#endif // RT30xx //


		#define BBPR94_DEFAULT 0x06 // Add 1 value will gain 1db
		@@ -1519,7 +1568,15 @@ typedef union _EEPROM_NIC_CINFIG2_STRUC {
		USHORT EnableWPSPBC:1; // WPS PBC Control bit
		USHORT BW40MAvailForG:1; // 0:enable, 1:disable
		USHORT BW40MAvailForA:1; // 0:enable, 1:disable
		#ifndef RT30xx
		USHORT Rsv2:6; // must be 0
		#endif
		#ifdef RT30xx
		USHORT Rsv1:1; // must be 0
		USHORT AntDiversity:1; // Antenna diversity
		USHORT Rsv2:3; // must be 0
		USHORT DACTestBit:1; // control if driver should patch the DAC issue
		#endif
		} field;
		USHORT word;
		} EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;