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Commit d1e3647d authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Update Superspeed PHY init sequence for kona"

parents 6d10a8b4 6f2fc4bf

qcom/kona-usb.dtsi

+29 −27
Original line number Diff line number Diff line
@@ -198,14 +198,14 @@ 
			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x05 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x60 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x60 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x11 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x02 0

			USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5 0

			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x54 0

			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0

			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x40 0

			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x06 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0

			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
@@ -216,7 +216,7 @@ 
			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x05 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x05 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0E 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0C 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
@@ -225,30 +225,30 @@ 
			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0

			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x7F 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xB7 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0xFF 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xB8 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x0B 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB3 0

			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0

			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0

			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0

			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0

			USB3_DP_QSERDES_RXA_GM_CAL 0x1F 0

			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x05 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x60 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x60 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x11 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x02 0

			USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5 0

			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x54 0

			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0

			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x06 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0

			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
@@ -259,7 +259,7 @@ 
			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x05 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x05 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0E 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0C 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
@@ -269,15 +269,15 @@ 
			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0

			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xB7 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x7F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0xFF 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xB8 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x97 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x0B 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB3 0

			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0

			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0

			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
@@ -289,7 +289,7 @@ 
			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0

			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0

			USB3_DP_PCS_RX_SIGDET_LVL 0xAA 0

			USB3_DP_PCS_RX_SIGDET_LVL 0xA9 0

			USB3_DP_PCS_CDR_RESET_TIME 0x0A 0

			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0

			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
@@ -505,7 +505,7 @@ 
		     USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xb8 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xff 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xb7 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xbf 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7f 0

		     USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0x7f 0

		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb4 0
@@ -541,15 +541,17 @@ 
		     USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0

		     USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0

		     USB3_UNI_QSERDES_TX_LANE_MODE_1 0xd5 0

		     USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82 0

		     USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x08 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x11 0

		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x02 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0

		     USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0

		     USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0

		     USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0

		     USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0

		     USB3_UNI_PCS_RX_SIGDET_LVL 0xa9 0

		     USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0

		     USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0

		     USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0