Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d1b2beb2 authored by Sravankumar bijili's avatar Sravankumar bijili
Browse files

msm: kgsl: Update CCU clock gating setting for A615 



Update CCU clock gating setting for A615 as per the
hardware requirement. New setting will disable clock
gating for color logic inside CCU.

Change-Id: If9219b499ca258fefd1b1148cf53235b82c61478
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: default avatarSravankumar bijili <csbijil@codeaurora.org>
parent f7be1951

drivers/gpu/msm/adreno-gpulist.h

+2 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2002,2007-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved.

 */



#define ANY_ID (~0)
@@ -835,7 +835,7 @@ static const struct adreno_reglist a615_hwcg_regs[] = { 
	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},

	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},

	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020},

	{A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},

	{A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},

	{A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},