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Commit d1a73602 authored by Shankar Ravi's avatar Shankar Ravi
Browse files

ARM: dts: qcom: Remove dependency for CSIPHY for lito 

CSPHY1, CSIPHY2, CSIPHY3 doesn't require CSIPHY0
dependecy clock as per hpg. Remove the dependency
clocks from the csiphy nodes.

Change-Id: I295803dfc550ad9d57bafa361d50b17448620230
parent 98b7ea97

qcom/lito-camera.dtsi

+9 −14
Original line number Diff line number Diff line
@@ -50,21 +50,19 @@ 
		csi-vdd-voltage = <880000>;

		mipi-csi-vdd-supply = <&L5A>;

		clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&camcc CAM_CC_CSIPHY0_CLK>,

			<&camcc CAM_CC_CSIPHY1_CLK>,

			<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,

			<&camcc CAM_CC_CSI1PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy0_clk",

			"csiphy1_clk",

			"csi1phytimer_clk_src",

			"csi1phytimer_clk";

		src-clock-name = "csi1phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs", "svs_l1";

		clock-rates =

			<300000000 0 0 300000000 0>,

			<384000000 0 0 300000000 0>,

			<400000000 0 0 300000000 0>;

			<300000000 0 300000000 0>,

			<384000000 0 300000000 0>,

			<400000000 0 300000000 0>;



		status = "ok";

	};
@@ -83,21 +81,19 @@ 
		csi-vdd-voltage = <880000>;

		mipi-csi-vdd-supply = <&L5A>;

		clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&camcc CAM_CC_CSIPHY0_CLK>,

			<&camcc CAM_CC_CSIPHY2_CLK>,

			<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,

			<&camcc CAM_CC_CSI2PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy0_clk",

			"csiphy2_clk",

			"csi2phytimer_clk_src",

			"csi2phytimer_clk";

		src-clock-name = "csi2phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs", "svs_l1";

		clock-rates =

			<300000000 0 0 300000000 0>,

			<384000000 0 0 300000000 0>,

			<400000000 0 0 300000000 0>;

			<300000000 0 300000000 0>,

			<384000000 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};
@@ -120,16 +116,15 @@ 
			<&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,

			<&camcc CAM_CC_CSI3PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy0_clk",

			"csiphy3_clk",

			"csi3phytimer_clk_src",

			"csi3phytimer_clk";

		src-clock-name = "csi3phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs", "svs_l1";

		clock-rates =

			<300000000 0 0 300000000 0>,

			<384000000 0 0 300000000 0>,

			<400000000 0 0 300000000 0>;

			<300000000 0 300000000 0>,

			<384000000 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};