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Commit d1877c0f authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Unify VLV/CHV DPOunit clock gating disable/enable 



Check for VLV/CHV instead if !BXT when re-enabling DPOunit clock gating
after DSI disable. That's what we checked when disabling the clock
gating when enabling DSI.

Also use the same temporary variable name in both cases, and toss in a
bit of dev vs. dev_priv cleanup while at it.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460996305-30453-1-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 64c050db

drivers/gpu/drm/i915/intel_dsi.c

+7 −6
Original line number Diff line number Diff line
@@ -516,7 +516,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder) 
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	enum port port;

	u32 tmp;



	DRM_DEBUG_KMS("\n");
@@ -535,11 +534,13 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder) 


	msleep(intel_dsi->panel_on_delay);



	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {

	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		u32 val;



		/* Disable DPOunit clock gating, can stall pipe */

		tmp = I915_READ(DSPCLK_GATE_D);

		tmp |= DPOUNIT_CLOCK_GATE_DISABLE;

		I915_WRITE(DSPCLK_GATE_D, tmp);

		val = I915_READ(DSPCLK_GATE_D);

		val |= DPOUNIT_CLOCK_GATE_DISABLE;

		I915_WRITE(DSPCLK_GATE_D, val);

	}



	/* put device in ready state */
@@ -677,7 +678,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder) 


	intel_dsi_clear_device_ready(encoder);



	if (!IS_BROXTON(dev_priv)) {

	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		u32 val;



		val = I915_READ(DSPCLK_GATE_D);