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Commit d14e72fb authored Apr 09, 2015 by Himanshu Madhani Committed by James Bottomley Apr 10, 2015

qla2xxx: Add debugging info for MBX timeout.



Signed-off-by: Giridhar Malavali <giridhar.malavali@qlogic.com>
Signed-off-by: Himanshu Madhani <himanshu.madhani@qlogic.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: James Bottomley <JBottomley@Odin.com>

parent 064135e0

drivers/scsi/qla2xxx/qla_dbg.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -11,7 +11,7 @@
		* ----------------------------------------------------------------------
		* \| Level \| Last Value Used \| Holes \|
		* ----------------------------------------------------------------------
		* \| Module Init and Probe \| 0x017d \| 0x0144,0x0146 \|
		* \| Module Init and Probe \| 0x017f \| 0x0146 \|
		* \| \| \| 0x015b-0x0160 \|
		* \| \| \| 0x016e-0x0170 \|
		* \| Mailbox commands \| 0x118d \| 0x1115-0x1116 \|

drivers/scsi/qla2xxx/qla_def.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -3300,6 +3300,8 @@ struct qla_hw_data {
		#define RISC_RDY_AFT_RESET 3
		#define RISC_SRAM_DUMP_CMPL 4
		#define RISC_EXT_MEM_DUMP_CMPL 5
		#define ISP_MBX_RDY 6
		#define ISP_SOFT_RESET_CMPL 7
		int fw_dump_reading;
		int prev_minidump_failed;
		dma_addr_t eft_dma;

drivers/scsi/qla2xxx/qla_init.c

+58 −10

Original line number	Diff line number	Diff line
		@@ -1121,7 +1121,7 @@ qla81xx_reset_mpi(scsi_qla_host_t *vha)
		*
		* Returns 0 on success.
		*/
		static inline void
		static inline int
		qla24xx_reset_risc(scsi_qla_host_t *vha)
		{
		unsigned long flags = 0;
		@@ -1130,6 +1130,7 @@ qla24xx_reset_risc(scsi_qla_host_t *vha)
		uint32_t cnt, d2;
		uint16_t wd;
		static int abts_cnt; /* ISP abort retry counts */
		int rval = QLA_SUCCESS;

		spin_lock_irqsave(&ha->hardware_lock, flags);

		@@ -1142,26 +1143,57 @@ qla24xx_reset_risc(scsi_qla_host_t *vha)
		udelay(10);
		}

		if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
		set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);

		ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
		"HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
		RD_REG_DWORD(&reg->hccr),
		RD_REG_DWORD(&reg->ctrl_status),
		(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));

		WRT_REG_DWORD(&reg->ctrl_status,
		CSRX_ISP_SOFT_RESET\|CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
		pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);

		udelay(100);

		/* Wait for firmware to complete NVRAM accesses. */
		d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
		for (cnt = 10000 ; cnt && d2; cnt--) {
		udelay(5);
		d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
		for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
		rval == QLA_SUCCESS; cnt--) {
		barrier();
		if (cnt)
		udelay(5);
		else
		rval = QLA_FUNCTION_TIMEOUT;
		}

		if (rval == QLA_SUCCESS)
		set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);

		ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
		"HCCR: 0x%x, MailBox0 Status 0x%x\n",
		RD_REG_DWORD(&reg->hccr),
		RD_REG_DWORD(&reg->mailbox0));

		/* Wait for soft-reset to complete. */
		d2 = RD_REG_DWORD(&reg->ctrl_status);
		for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
		udelay(5);
		d2 = RD_REG_DWORD(&reg->ctrl_status);
		for (cnt = 0; cnt < 6000000; cnt++) {
		barrier();
		if ((RD_REG_DWORD(&reg->ctrl_status) &
		CSRX_ISP_SOFT_RESET) == 0)
		break;

		udelay(5);
		}
		if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
		set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);

		ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
		"HCCR: 0x%x, Soft Reset status: 0x%x\n",
		RD_REG_DWORD(&reg->hccr),
		RD_REG_DWORD(&reg->ctrl_status));

		/* If required, do an MPI FW reset now */
		if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
		@@ -1190,16 +1222,32 @@ qla24xx_reset_risc(scsi_qla_host_t *vha)
		RD_REG_DWORD(&reg->hccr);

		d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
		for (cnt = 6000000 ; cnt && d2; cnt--) {
		udelay(5);
		d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
		for (cnt = 6000000; RD_REG_WORD(&reg->mailbox0) != 0 &&
		rval == QLA_SUCCESS; cnt--) {
		barrier();
		if (cnt)
		udelay(5);
		else
		rval = QLA_FUNCTION_TIMEOUT;
		}
		if (rval == QLA_SUCCESS)
		set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);

		ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
		"Host Risc 0x%x, mailbox0 0x%x\n",
		RD_REG_DWORD(&reg->hccr),
		RD_REG_WORD(&reg->mailbox0));

		spin_unlock_irqrestore(&ha->hardware_lock, flags);

		ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
		"Driver in %s mode\n",
		IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");

		if (IS_NOPOLLING_TYPE(ha))
		ha->isp_ops->enable_intrs(ha);

		return rval;
		}

		static void

drivers/scsi/qla2xxx/qla_mbx.c

+15 −1

Original line number	Diff line number	Diff line
		@@ -33,7 +33,7 @@
		static int
		qla2x00_mailbox_command(scsi_qla_host_t vha, mbx_cmd_t mcp)
		{
		int rval;
		int rval, i;
		unsigned long flags = 0;
		device_reg_t *reg;
		uint8_t abort_active;
		@@ -43,10 +43,12 @@ qla2x00_mailbox_command(scsi_qla_host_t vha, mbx_cmd_t mcp)
		uint16_t __iomem *optr;
		uint32_t cnt;
		uint32_t mboxes;
		uint16_t __iomem *mbx_reg;
		unsigned long wait_time;
		struct qla_hw_data *ha = vha->hw;
		scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);


		ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);

		if (ha->pdev->error_state > pci_channel_io_frozen) {
		@@ -376,6 +378,18 @@ qla2x00_mailbox_command(scsi_qla_host_t vha, mbx_cmd_t mcp)
		ql_dbg(ql_dbg_disc, base_vha, 0x1020,
		"** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x **.\n",
		mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);

		ql_dbg(ql_dbg_disc, vha, 0x1115,
		"host status: 0x%x, flags:0x%lx, intr ctrl reg:0x%x, intr status:0x%x\n",
		RD_REG_DWORD(&reg->isp24.host_status),
		ha->fw_dump_cap_flags,
		RD_REG_DWORD(&reg->isp24.ictrl),
		RD_REG_DWORD(&reg->isp24.istatus));

		mbx_reg = &reg->isp24.mailbox0;
		for (i = 0; i < 6; i++)
		ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x1116,
		"mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
		} else {
		ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
		}