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Commit d132ec2c authored by Bjorn Helgaas's avatar Bjorn Helgaas Committed by Greg Kroah-Hartman
Browse files

PCI: Cleanup register definition width and whitespace 



[ Upstream commit 35d0a06dad2220d62042fd1a91a216d17744e724 ]

Follow the file conventions of:

  - register offsets not indented
  - fields within a register indented one space
  - field masks use same width as register
  - register field values indented an additional space

No functional change intended.

Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Stable-dep-of: ce7d88110b9e ("drm/amdgpu: Use RMW accessors for changing LNKCTL")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 9697498a

include/uapi/linux/pci_regs.h

+65 −67
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */

/*

 *	pci_regs.h

 *

 *	PCI standard defines

 *	Copyright 1994, Drew Eckhardt

 *	Copyright 1997--1999 Martin Mares <mj@ucw.cz>
@@ -15,7 +13,7 @@ 
 *	PCI System Design Guide

 *

 *	For HyperTransport information, please consult the following manuals

 *	from http://www.hypertransport.org

 *	from http://www.hypertransport.org :

 *

 *	The HyperTransport I/O Link Specification

 */
@@ -300,7 +298,7 @@ 
#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */

#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */



/* Message Signalled Interrupts registers */

/* Message Signalled Interrupt registers */



#define PCI_MSI_FLAGS		2	/* Message Control */

#define  PCI_MSI_FLAGS_ENABLE	0x0001	/* MSI feature enabled */
@@ -318,7 +316,7 @@ 
#define PCI_MSI_MASK_64		16	/* Mask bits register for 64-bit devices */

#define PCI_MSI_PENDING_64	20	/* Pending intrs for 64-bit devices */



/* MSI-X registers */

/* MSI-X registers (in MSI-X capability) */

#define PCI_MSIX_FLAGS		2	/* Message Control */

#define  PCI_MSIX_FLAGS_QSIZE	0x07FF	/* Table size */

#define  PCI_MSIX_FLAGS_MASKALL	0x4000	/* Mask all vectors for this function */
@@ -332,13 +330,13 @@ 
#define PCI_MSIX_FLAGS_BIRMASK	PCI_MSIX_PBA_BIR /* deprecated */

#define PCI_CAP_MSIX_SIZEOF	12	/* size of MSIX registers */



/* MSI-X Table entry format */

/* MSI-X Table entry format (in memory mapped by a BAR) */

#define PCI_MSIX_ENTRY_SIZE		16

#define  PCI_MSIX_ENTRY_LOWER_ADDR	0

#define  PCI_MSIX_ENTRY_UPPER_ADDR	4

#define  PCI_MSIX_ENTRY_DATA		8

#define  PCI_MSIX_ENTRY_VECTOR_CTRL	12

#define   PCI_MSIX_ENTRY_CTRL_MASKBIT	1

#define PCI_MSIX_ENTRY_LOWER_ADDR	0  /* Message Address */

#define PCI_MSIX_ENTRY_UPPER_ADDR	4  /* Message Upper Address */

#define PCI_MSIX_ENTRY_DATA		8  /* Message Data */

#define PCI_MSIX_ENTRY_VECTOR_CTRL	12 /* Vector Control */

#define  PCI_MSIX_ENTRY_CTRL_MASKBIT	0x00000001



/* CompactPCI Hotswap Register */
@@ -879,12 +877,12 @@ 


/* Page Request Interface */

#define PCI_PRI_CTRL		0x04	/* PRI control register */

#define  PCI_PRI_CTRL_ENABLE	0x01	/* Enable */

#define  PCI_PRI_CTRL_RESET	0x02	/* Reset */

#define  PCI_PRI_CTRL_ENABLE	0x0001	/* Enable */

#define  PCI_PRI_CTRL_RESET	0x0002	/* Reset */

#define PCI_PRI_STATUS		0x06	/* PRI status register */

#define  PCI_PRI_STATUS_RF	0x001	/* Response Failure */

#define  PCI_PRI_STATUS_UPRGI	0x002	/* Unexpected PRG index */

#define  PCI_PRI_STATUS_STOPPED	0x100	/* PRI Stopped */

#define  PCI_PRI_STATUS_RF	0x0001	/* Response Failure */

#define  PCI_PRI_STATUS_UPRGI	0x0002	/* Unexpected PRG index */

#define  PCI_PRI_STATUS_STOPPED	0x0100	/* PRI Stopped */

#define  PCI_PRI_STATUS_PASID	0x8000	/* PRG Response PASID Required */

#define PCI_PRI_MAX_REQ		0x08	/* PRI max reqs supported */

#define PCI_PRI_ALLOC_REQ	0x0c	/* PRI max reqs allowed */
@@ -902,16 +900,16 @@ 


/* Single Root I/O Virtualization */

#define PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */

#define  PCI_SRIOV_CAP_VFM	0x01	/* VF Migration Capable */

#define  PCI_SRIOV_CAP_VFM	0x00000001  /* VF Migration Capable */

#define  PCI_SRIOV_CAP_INTR(x)	((x) >> 21) /* Interrupt Message Number */

#define PCI_SRIOV_CTRL		0x08	/* SR-IOV Control */

#define  PCI_SRIOV_CTRL_VFE	0x01	/* VF Enable */

#define  PCI_SRIOV_CTRL_VFM	0x02	/* VF Migration Enable */

#define  PCI_SRIOV_CTRL_INTR	0x04	/* VF Migration Interrupt Enable */

#define  PCI_SRIOV_CTRL_MSE	0x08	/* VF Memory Space Enable */

#define  PCI_SRIOV_CTRL_ARI	0x10	/* ARI Capable Hierarchy */

#define  PCI_SRIOV_CTRL_VFE	0x0001	/* VF Enable */

#define  PCI_SRIOV_CTRL_VFM	0x0002	/* VF Migration Enable */

#define  PCI_SRIOV_CTRL_INTR	0x0004	/* VF Migration Interrupt Enable */

#define  PCI_SRIOV_CTRL_MSE	0x0008	/* VF Memory Space Enable */

#define  PCI_SRIOV_CTRL_ARI	0x0010	/* ARI Capable Hierarchy */

#define PCI_SRIOV_STATUS	0x0a	/* SR-IOV Status */

#define  PCI_SRIOV_STATUS_VFM	0x01	/* VF Migration Status */

#define  PCI_SRIOV_STATUS_VFM	0x0001	/* VF Migration Status */

#define PCI_SRIOV_INITIAL_VF	0x0c	/* Initial VFs */

#define PCI_SRIOV_TOTAL_VF	0x0e	/* Total VFs */

#define PCI_SRIOV_NUM_VF	0x10	/* Number of VFs */
@@ -941,13 +939,13 @@ 


/* Access Control Service */

#define PCI_ACS_CAP		0x04	/* ACS Capability Register */

#define  PCI_ACS_SV		0x01	/* Source Validation */

#define  PCI_ACS_TB		0x02	/* Translation Blocking */

#define  PCI_ACS_RR		0x04	/* P2P Request Redirect */

#define  PCI_ACS_CR		0x08	/* P2P Completion Redirect */

#define  PCI_ACS_UF		0x10	/* Upstream Forwarding */

#define  PCI_ACS_EC		0x20	/* P2P Egress Control */

#define  PCI_ACS_DT		0x40	/* Direct Translated P2P */

#define  PCI_ACS_SV		0x0001	/* Source Validation */

#define  PCI_ACS_TB		0x0002	/* Translation Blocking */

#define  PCI_ACS_RR		0x0004	/* P2P Request Redirect */

#define  PCI_ACS_CR		0x0008	/* P2P Completion Redirect */

#define  PCI_ACS_UF		0x0010	/* Upstream Forwarding */

#define  PCI_ACS_EC		0x0020	/* P2P Egress Control */

#define  PCI_ACS_DT		0x0040	/* Direct Translated P2P */

#define PCI_ACS_EGRESS_BITS	0x05	/* ACS Egress Control Vector Size */

#define PCI_ACS_CTRL		0x06	/* ACS Control Register */

#define PCI_ACS_EGRESS_CTL_V	0x08	/* ACS Egress Control Vector */