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Commit d126e86f authored by Pierre-Yves MORDRET's avatar Pierre-Yves MORDRET Committed by Alexandre Torgue
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ARM: dts: stm32: Add STM32F7 I2C support for STM32MP157C SoC 



This patch adds all STM32F7 I2C instances for STM32MP157C SoC.

Signed-off-by: default avatarPierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: default avatarAlexandre Torgue <alexandre.torgue@st.com>
parent 8b2820ab

arch/arm/boot/dts/stm32mp157c.dtsi

+78 −0
Original line number Diff line number Diff line
@@ -343,6 +343,58 @@ 
			status = "disabled";

		};



		i2c1: i2c@40012000 {

			compatible = "st,stm32f7-i2c";

			reg = <0x40012000 0x400>;

			interrupt-names = "event", "error";

			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc I2C1_K>;

			resets = <&rcc I2C1_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		i2c2: i2c@40013000 {

			compatible = "st,stm32f7-i2c";

			reg = <0x40013000 0x400>;

			interrupt-names = "event", "error";

			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc I2C2_K>;

			resets = <&rcc I2C2_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		i2c3: i2c@40014000 {

			compatible = "st,stm32f7-i2c";

			reg = <0x40014000 0x400>;

			interrupt-names = "event", "error";

			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc I2C3_K>;

			resets = <&rcc I2C3_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		i2c5: i2c@40015000 {

			compatible = "st,stm32f7-i2c";

			reg = <0x40015000 0x400>;

			interrupt-names = "event", "error";

			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc I2C5_K>;

			resets = <&rcc I2C5_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		dac: dac@40017000 {

			compatible = "st,stm32h7-dac-core";

			reg = <0x40017000 0x400>;
@@ -673,5 +725,31 @@ 
			clocks = <&rcc USART1_K>;

			status = "disabled";

		};



		i2c4: i2c@5c002000 {

			compatible = "st,stm32f7-i2c";

			reg = <0x5c002000 0x400>;

			interrupt-names = "event", "error";

			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc I2C4_K>;

			resets = <&rcc I2C4_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		i2c6: i2c@5c009000 {

			compatible = "st,stm32f7-i2c";

			reg = <0x5c009000 0x400>;

			interrupt-names = "event", "error";

			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc I2C6_K>;

			resets = <&rcc I2C6_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};

	};

};