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Commit d1048aaf authored by Huang Shijie's avatar Huang Shijie Committed by David Woodhouse
Browse files

mtd: add the ecc info for some full-id nand chips 



Add the ecc info for TC58NVG2S0F, TC58NVG3S0F, TC58NVG5D2 and TC58NVG6D2.

From these chips' datasheets, we know that:
   The TC58NVG2S0F and TC58NVG3S0F require 4bit ECC for per 512byte.
   The TC58NVG5D2 and TC58NVG6D2 require 40bits ECC for per 1024byte.

Signed-off-by: default avatarHuang Shijie <b32955@freescale.com>
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
Signed-off-by: default avatarDavid Woodhouse <David.Woodhouse@intel.com>
parent 57219342

drivers/mtd/nand/nand_ids.c

+4 −4
Original line number Diff line number Diff line
@@ -33,16 +33,16 @@ struct nand_flash_dev nand_flash_ids[] = { 
	 */

	{"TC58NVG2S0F 4G 3.3V 8-bit",

		{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },

		  SZ_4K, SZ_512, SZ_256K, 0, 8, 224},

		  SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },

	{"TC58NVG3S0F 8G 3.3V 8-bit",

		{ .id = {0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08} },

		  SZ_4K, SZ_1K, SZ_256K, 0, 8, 232},

		  SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },

	{"TC58NVG5D2 32G 3.3V 8-bit",

		{ .id = {0x98, 0xd7, 0x94, 0x32, 0x76, 0x56, 0x09, 0x00} },

		  SZ_8K, SZ_4K, SZ_1M, 0, 8, 640},

		  SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },

	{"TC58NVG6D2 64G 3.3V 8-bit",

		{ .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} },

		  SZ_8K, SZ_8K, SZ_2M, 0, 8, 640},

		  SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },



	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),

	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),