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Commit d0f5c748 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "disp: msm: assert nrt vbif halt req as part of rscc mode2 sequence"

parents b14ec0e0 bf0929a5

msm/sde_rsc_hw_v3.c

+6 −6
Original line number Diff line number Diff line
@@ -106,17 +106,17 @@ static int _rsc_hw_seq_memory_init_v3(struct sde_rsc_priv *rsc) 


	/* Mode - 2 sequence */

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x18,

						0xbdf9b9a0, rsc->debug_mode);

						0xf9b9baa0, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x1c,

						0xa13899fe, rsc->debug_mode);

						0x999afebd, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x20,

						0xe0ac81e1, rsc->debug_mode);

						0x81e1a138, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x24,

						0x3982e2a2, rsc->debug_mode);

						0xe2a2e0ac, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x28,

						0x208cfd9d, rsc->debug_mode);

						0xfd9d3982, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x2c,

						0x20202020, rsc->debug_mode);

						0x2020208c, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x30,

						0x20202020, rsc->debug_mode);